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From solid-state storage drives to automotive control and artificial intelligence (AI) at the edge, an array of embedded applications is demanding increasingly higher performance. In answer to these demands, processors are getting more complex, with chip designers squeezing every last megahertz and every last drop of energy from them—all while under tight time-to-market pressures.
What’s the most effective and efficient way to optimize a high-performance processor implementation for a multi-core SoC?
In this blog post, we’ll introduce new implementation kits that can give you a head start in the development process for high-performance embedded processors. With an assist from an AI-based SoC design tool, the 草榴社区 Fusion QuickStart Implementation Kits (QIKs) generate better power, performance, and area (PPA) from your processor with a faster time-to-market for integration into your SoC.
You can also learn more about these new QIKs, which are now available, from our session at the upcoming ARC Processor Summit 2022 on September 8 at the Santa Clara Marriott hotel in Santa Clara, California. In “Optimize High-Performance Processor Implementation with AI-Enabled Fusion QuickStart Kit,” you’ll find out how the QIKs provide an ideal starting point for implementing 草榴社区 ARC? HS68 64-bit processors for high-performance embedded designs.
What are High-Performance Embedded Applications?
Let’s first provide an overview of high-performance embedded applications, which typically encompass those that require a large amount of compute resources. Some key examples include:
- Solid-state drive (SSD) storage, marked by rapidly increasing drive capacity, the need for high bandwidth and low latency, and in-storage compute and AI.
- Networking, where intelligence is distributed across the network, processing and storage happens at each compute node, and higher bandwidth and more data processing are needed.
- AI, particularly as machine learning inference moves to the edge where data must be captured, processed, and acted upon without the latency of going to/from the cloud. Specialized execution hardware and very high memory bandwidth are key requirements.
- Wireless, particularly as 5G becomes more prevalent. These applications are marked by high data rates and low latency, with rapidly changing data processing requirements.
- Automotive, where real-time response times and functional safety features require high throughput and add design and layout complexity.
The slowing of Moore’s law has limited the ability to generate higher performance by cranking up clock frequency or moving to smaller geometries. Modern processor architectures have evolved to address these limitations by taking advantage of parallelism – doing more work in the same amount of time. For example, single instruction/multiple data (SIMD) instructions enable the processor to operate on many data items in parallel; similarly, superscalar designs take advantage of instruction-level parallelism but fetching and executing multiple instructions simultaneously. In addition, some processors enable users to create custom commands, extending the instruction set to optimize the execution of specific, often-used software algorithms. These advanced processor architectures can, however, increase design complexity and make implementation and integration into an SoC more challenging.
One such modern processor is the ARC HS68, the latest addition to the ARC CPU Processor IP family. It’s based on 草榴社区’ advanced ARCv3 Instruction Set Architecture (ISA) and pipeline, designed to deliver power efficiency and code density as well as high performance. The ARC HS68 processor features a dual-issue, superscalar 64-bit architecture that supports 52-bit physical and 64-bit virtual addresses, making the processors ideally suited for embedded applications that require high throughput. The processors deliver exceptional single core (CoreMark?/MHz) and multi-core performance with a small footprint and low power consumption.
Get Your SoC Up and Running Faster
To optimize a processor for a specific application’s PPA goals, savvy engineers would need to put in a lot of manual effort, writing tool scripts and performing multiple iterations to hit the right targets before integrating the processor into an SoC. It’s a time-consuming process that many can’t afford, given their aggressive time-to-market goals. Enter the QIKs. With these productivity-enhancing kits, our engineers—IP, tool, and flow experts—have done all the legwork.
Our newest QIKs are for the ARC HS5x (32-bit) and HS6x (64-bit) processors. QIKs include tool scripts, a baseline floorplan, design constraints, and documentation. Fusion QIKs make use of 草榴社区 Fusion Compiler RTL-to-GDSII design product and 草榴社区 Design Space Optimization (DSO.ai?) AI application for chip design to achieve optimal PPA and faster time-to-market. The Fusion Compiler solution helps push performance levels higher, while DSO.ai technology autonomously explores multiple design spaces to optimize PPA metrics while minimizing tradeoffs for the target application.
Summary
High-performance embedded applications such as storage, networking, and automotive will continue to demand more performance and better power efficiency. Processors supporting these applications, meanwhile, are becoming more complex and market windows continue to compress. By offering pre-validated tool scripts and documentation, 草榴社区’ QIKs provide SoC designers with trusted and proven implementation recipes that have been thoroughly vetted by 草榴社区 engineers, increasing design confidence, improving time-to-market, and accelerating the time to reach the desired PPA goals.
See Us at ARC Processor Summit
We look forward to continuing the discussion with you at our session at the ARC Processor Summit on September 8, 2022. The summit starts at 9:30a.m. and features tracks on automotive, AI, and enabling technologies. The sessions will be followed by a networking reception where you can see live demos and chat with other attendees, 草榴社区 partners, and our technical experts. Register today!