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Achieving Faster Sign Off with Targeted Setting Execution in PCIe Polling Compliance Load Board Verification
Key Highlights:
- Overcome the challenges of PCIe 6.0+ compliance load board testing with a targeted approach.
- Reduce debugging time by directly accessing specific compliance load board settings.
- Ensure efficient and scalable verification for future PCIe generations.
- Learn how 草榴社区 Verification IP (VIP) solutions can accelerate your PCIe verification process.
In today's rapidly evolving technological landscape, high-speed data transfer is essential for various applications, especially in AI/ML SoCs. PCIe has emerged as a leading standard for high-speed interconnects, with each new generation pushing the boundaries of data rates and complexity. However, verifying that designs comply with the latest PCIe specifications, particularly for PCIe 6.0+, poses significant challenges for verification engineers. This blog post explores the complexities of PCIe compliance load board testing and introduces a targeted approach that can significantly accelerate the verification process.
Polling Compliance LTSSM State
In PCI Express, the Polling Compliance state is a crucial part of the Link Training and Status State Machine (LTSSM), serving as a dedicated phase for compliance testing. This state verifies a device's electrical and protocol-level behavior, ensuring it adheres to PCIe specifications.
- The LTSSM transitions to Polling Compliance from Polling Active if:
- The Enter Compliance bit (bit 4) in the Link Control 2 Register is set to 1b.
- After a 24ms timeout:
- Eight consecutive TS1 Ordered Sets are received with Compliance_Receive_Request asserted and Loopback_Request deasserted.
- Not all lanes have detected an exit from Electrical Idle (Compliance Load Board Mode)
During PCIe Compliance Load Board testing, the device under test (DUT) goes through a series of defined settings. The specific data rate, transmitter preset, and de-emphasis level for each setting are determined by the device's maximum supported data rate and the number of times the Polling Compliance state has been entered. These settings follow a strict order outlined in the PCIe specification with total number of settings as 167 for PCIe 7.0.
For each setting, the transmitter sends out patterns on the lanes that have detected a receiver. These patterns vary depending on the specific setting number. The patterns can include:
- Compliance Pattern: Sent on all lanes for many of the initial settings.
- Jitter Measurement Pattern: Sent on all lanes for certain settings, and on specific lanes (e.g., 0/8, 1/9, etc.) for other settings, with the Compliance Pattern on the remaining lanes.
- High Swing Toggle Pattern: Sent on all lanes for some settings, and on specific lanes (e.g., 0/8, 1/9, etc.) for other settings, with the Compliance Pattern on the remaining lanes.
- Low Swing Toggle Pattern: Sent on all lanes for setting #84.
- LSTPx Patterns (where x is 0,1,2,3,4): Sent on all lanes for some settings and on specific lanes for other settings, with the Compliance Pattern on the remaining lanes for other settings.
- SHSTP Pattern: Sent on all lanes for setting #159 and on specific lanes with the Compliance Pattern on the remaining lanes for other settings.
This process ensures that the DUT is thoroughly tested under various signal conditions and patterns, validating its compliance with the PCIe specifications.
The PCIe Compliance Load Board Testing Bottleneck
Problem Statement: PCIe compliance load board testing requires executing many load board settings to ensure a Device Under Test's (DUT) compliance with the PCIe standard. This applies to verifying different types of DUTs, such as Endpoint (EP) devices and Root Complex (RC) devices. A significant challenge in Design Verification is the lengthy turnaround time associated with testing these numerous settings, especially when debugging a setting where the behavior is not as expected. Therefore, a key objective is to optimize this process to accelerate verification and reduce the time required to validate this feature across various DUT types. The number of these settings have increased dramatically from PCIe 5.0 to PCIe 7.0, leading to longer verification cycles.
PCIe Version Number of Settings
PCIe 5.0 54
PCIe 6.0 84
PCIe 7.0 167
- Entry to Polling Compliance: The link enters the Polling Compliance LTSSM state from the Polling Active LTSSM state via timeout, starting at 2.5 GT/s speed.
- Data Rate Increase: During Polling Compliance, the data rate is increased to the next higher speed, and the setting number is incremented.
- Pattern Transmission: The device transmits a pattern based on the current speed and the updated setting number, as defined by the PCIe specification.
- Exit to Polling Active: The test directs the link to transition out of Polling Compliance and return to the Polling Active state.
- Repeat Cycle: The link re-enters the Polling Compliance LTSSM state from the Polling Active LTSSM state via another timeout, again at 2.5 GT/s speed.
- Further Data Rate Increase: During this subsequent Polling Compliance phase, the data rate is further increased to the next higher rate, and the setting number is incremented again.
- New Pattern Transmission: The device transmits a new pattern based on the new speed and the updated setting number, following the PCIe specification.
- Repeat Exit: The test directs the link to exit Polling Compliance and return to Polling Active.
- Continued Iteration: This entire process repeats continuously until the highest setting number is reached, which depends on the PCIe version:
- 54 for PCIe 5.0
- 84 for PCIe 6.0
- 167 for PCIe 7.0
Traditional sequential execution of all settings, as mandated by the PCIe specification, results in substantial time wastage, especially when debugging specific settings.
If the behavior is not as expected at a specific setting, engineers must simulate all preceding settings before reaching the target—a highly inefficient and time-consuming approach. This challenge is particularly critical for PCIe 6.0+, where newly introduced settings are more prone to ambiguities and misinterpretations. Traditional sequential execution increases debugging overhead, slowing down verification and extending product development timelines.
Positive Outcome Expected: A solution that allows engineers to directly access and verify specific compliance load board settings, bypassing unnecessary sequential steps, would significantly reduce debugging time and accelerate the verification process.
Impact of Positive Outcome: Faster verification cycles would enable faster time-to-market, reduced development costs, and improved product quality.
Targeted Compliance Load Board Verification
Current State of Things: Traditional PCIe compliance load board verification involves sequential execution of all load board settings, which is time-consuming and inefficient when debugging specific settings.
Gaps in Current specification defined approach: The lack of a mechanism to directly access and verify specific compliance load board settings leads to wasted time and resources.
Challenges Arising from Gaps: Increased debugging overhead, slower verification cycles, and extended product development timelines as outlined in the next section.
草榴社区 Solution
Solution Details: A smart Compliance Load Board Verification technique has been developed that employs a user-configurable control mechanism. This mechanism allows engineers to customize the execution sequence of compliance settings to meet their specific needs and debugging scenarios. By selectively enabling or disabling individual settings, engineers gain fine-grained control over the verification process.
Key Metrics/Results: This targeted approach has demonstrated a significant improvement in debugging time compared to conventional sequential verification.
Consider an engineer debugging compliance setting #84. Using the traditional method, he must simulate all 83 preceding settings before reaching #84, wasting valuable debugging time.
Using this targeted execution method, selectively activating setting #84 allowed for an immediate jump to that specific test, bypassing all preceding settings. This greatly reduced the time (by ~10x) needed to reach and analyze the target setting.
Method Simulation Time to Setting #84 CPU Time
Traditional Execution 1543.47?s 1333.88s
Targeted Execution 28.86?s 130.66s
By eliminating redundant test steps, this approach:
? Accelerates compliance testing, reducing execution time.
? Improves debugging accuracy, enabling engineers to focus on high-risk settings.
? Optimizes resource usage, reducing CPU time and simulation overhead.
? Scales efficiently, supporting future PCIe generations with expanded compliance requirements.
Traditional Execution:
Targeted Execution:
Forward Looking - What Next?
As PCIe technology continues to evolve, the number of compliance requirements is expected to increase. This underscores the critical need for scalable and efficient verification solutions. 草榴社区 remains dedicated to developing innovative verification technologies that address these challenges.
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