Jun 13, 2024/2 min read Verdi Waveform Utilities: Get More Done with Faster Runtime and Less Memory By Lauren Wu, Robert Ruiz Tags: Verification Central, Debug, Verification
May 09, 2024/3 min read Interactive Debugging: Reduce Your Simulation Debug Turnaround Time By Vita Liao Tags: Verification Central, Debug, Simulation, Verification
Mar 08, 2024/9 min read SoC Design and Verification 草榴社区 for a New Era of AI Chips By Kiran Vittal Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification
Feb 07, 2024/5 min read A Pain in the X! Why Debugging Xs can be Difficult By Myles Gilsson Tags: Verification Central, Debug, Verification
Jul 12, 2023/2 min read Streamline Projects with Verdi and VCS Coverage Tools By Taruna Reddy Tags: Verification Central, Debug, Simulation, Verification, Formal Verification
May 03, 2023/6 min read How Imparé Leverages Chip Design Verification in the Cloud By Rob van Blommestein Tags: Customer Spotlight, Cloud, Debug, Chip Design Insights, Simulation, Verification
Mar 09, 2023/5 min read Optimizing the RTL Design Flow with Real-Time PPA Analysis By Jim Schultz Tags: RTL Synthesis, Product Spotlight, Debug, Chip Design Insights, Design, Verification
Feb 15, 2023/4 min read Enhancing Chip Design Simulation with AI By Taruna Reddy Tags: AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, Verification
Dec 15, 2022/2 min read How to Achieve 2X Faster Waveform Dumping in 草榴社区 Verdi with VCS By Taruna Reddy Tags: Verification Central, Debug, Simulation, Verification
Nov 15, 2022/3 min read Exploring ML-Based Regression Failure Analysis By Rob van Bloomestein Tags: Verification Central, Debug, Verification
Oct 24, 2022/6 min read Advanced Protocol Standards Verification for SoC Designs? By Vikas Gautam Tags: Debug, Prototyping, Chip Design Insights, Emulation, Interface IP, Verification IP, Silicon IP, Verification
Sep 11, 2022/2 min read AI-Driven Debug Automation Speeds Up Root-Cause Analysis? By Rob van Blommestein Tags: AI & Machine Learning, Debug, Chip Design Insights, Design, Verification
Jul 12, 2022/4 min read Enhancing Chip Verification with AI & Machine Learning By Rob van Blommestein Tags: Multi-Die System, Static Verification, AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, HPC, Data Center, Verification, Formal Verification
Jun 01, 2022/6 min read Fault Simulation Techniques for Growing Chip Complexity By Brian Davenport, Rimpy Chugh Tags: Customer Spotlight, Aerospace & Government, Debug, Chip Design Insights, Simulation, Automotive, Verification
Mar 20, 2022/4 min read Boosting EDA Workloads with 3rd Gen AMD EPYC? Processors? By Ramesh Narayanaswamy Tags: Customer Spotlight, Debug, Chip Design Insights, Simulation, Verification
Jan 17, 2022/4 min read Accelerating System Debug in the SoC Verification Flow? By Swami Venkat, Taruna Reddy Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification
Nov 22, 2021/7 min read What is Clock Domain Crossing? - ASIC Design Challenges? By Rimpy Chugh Tags: Debug, Chip Design Insights, Simulation, Verification
Nov 21, 2021/5 min read Functional Chip Design Verification: When Is It Truly Finished?? By Will Chen, Anika Malhotra Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification IP, Verification
Nov 10, 2021/7 min read Advancing Women in Tech Careers: Q&A with Latha Venkatachari By 草榴社区 Editorial Staff Tags: Debug, Chip Design Insights, Verification, Inside 草榴社区, Formal Verification
Oct 26, 2021/7 min read ASIC Hardware Verification: Debug Challenges & 草榴社区? By Kiran Vittal Tags: Debug, Prototyping, Chip Design Insights, Emulation, Verification, Virtual Prototyping, Formal Verification
Oct 06, 2021/5 min read RTL Debugging via FPGA Prototyping: SoC Design Challenges? By Rob Parris Tags: Debug, Prototyping, Chip Design Insights, Verification
Sep 20, 2021/5 min read Upgrading FPGA Prototyping for RTL Debug Productivity By Rob Parris Tags: Debug, Prototyping, Chip Design Insights, Verification
Feb 23, 2021/5 min read Verifying Complex Datapath Designs with HECTOR? By Kiran Vittal, Alfred Koelbl, Pratik Mahajan Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification