BLOG 2 min read/Jun 13, 2024 BLOG Verdi Waveform Utilities: Get More Done with Faster Runtime and Less Memory By Lauren Wu, Robert Ruiz Tags: Verification Central, Debug, Verification
BLOG 3 min read/May 09, 2024 BLOG Interactive Debugging: Reduce Your Simulation Debug Turnaround Time By Vita Liao Tags: Verification Central, Debug, Simulation, Verification
BLOG 9 min read/Mar 08, 2024 BLOG SoC Design and Verification 草榴社区 for a New Era of AI Chips By Kiran Vittal Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification
BLOG 5 min read/Feb 07, 2024 BLOG A Pain in the X! Why Debugging Xs can be Difficult By Myles Gilsson Tags: Verification Central, Debug, Verification
BLOG 2 min read/Jul 12, 2023 BLOG Streamline Projects with Verdi and VCS Coverage Tools By Taruna Reddy Tags: Verification Central, Debug, Simulation, Verification, Formal Verification
BLOG 6 min read/May 03, 2023 BLOG How Imparé Leverages Chip Design Verification in the Cloud By Rob van Blommestein Tags: Customer Spotlight, Cloud, Debug, Chip Design Insights, Simulation, Verification
BLOG 5 min read/Mar 09, 2023 BLOG Optimizing the RTL Design Flow with Real-Time PPA Analysis By Jim Schultz Tags: RTL Synthesis, Product Spotlight, Debug, Chip Design Insights, Design, Verification
BLOG 4 min read/Feb 15, 2023 BLOG Enhancing Chip Design Simulation with AI By Taruna Reddy Tags: AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, Verification
BLOG 2 min read/Dec 15, 2022 BLOG How to Achieve 2X Faster Waveform Dumping in 草榴社区 Verdi with VCS By Taruna Reddy Tags: Verification Central, Debug, Simulation, Verification
BLOG 3 min read/Nov 15, 2022 BLOG Exploring ML-Based Regression Failure Analysis By Rob van Bloomestein Tags: Verification Central, Debug, Verification
BLOG 6 min read/Oct 24, 2022 BLOG Advanced Protocol Standards Verification for SoC Designs? By Vikas Gautam Tags: Debug, Prototyping, Chip Design Insights, Emulation, Interface IP, Verification IP, Silicon IP, Verification
BLOG 2 min read/Sep 11, 2022 BLOG AI-Driven Debug Automation Speeds Up Root-Cause Analysis? By Rob van Blommestein Tags: AI & Machine Learning, Debug, Chip Design Insights, Design, Verification
BLOG 4 min read/Jul 12, 2022 BLOG Enhancing Chip Verification with AI & Machine Learning By Rob van Blommestein Tags: Multi-Die System, Static Verification, AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, HPC, Data Center, Verification, Formal Verification
BLOG 6 min read/Jun 01, 2022 BLOG Fault Simulation Techniques for Growing Chip Complexity By Brian Davenport, Rimpy Chugh Tags: Customer Spotlight, Aerospace & Government, Debug, Chip Design Insights, Simulation, Automotive, Verification
BLOG 4 min read/Mar 20, 2022 BLOG Boosting EDA Workloads with 3rd Gen AMD EPYC? Processors? By Ramesh Narayanaswamy Tags: Customer Spotlight, Debug, Chip Design Insights, Simulation, Verification
BLOG 4 min read/Jan 17, 2022 BLOG Accelerating System Debug in the SoC Verification Flow? By Swami Venkat, Taruna Reddy Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification
BLOG 7 min read/Nov 22, 2021 BLOG What is Clock Domain Crossing? - ASIC Design Challenges? By Rimpy Chugh Tags: Debug, Chip Design Insights, Simulation, Verification
BLOG 5 min read/Nov 21, 2021 BLOG Functional Chip Design Verification: When Is It Truly Finished?? By Will Chen, Anika Malhotra Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification IP, Verification
BLOG 7 min read/Nov 10, 2021 BLOG Advancing Women in Tech Careers: Q&A with Latha Venkatachari By 草榴社区 Editorial Staff Tags: Debug, Chip Design Insights, Verification, Inside 草榴社区, Formal Verification
BLOG 7 min read/Oct 26, 2021 BLOG ASIC Hardware Verification: Debug Challenges & 草榴社区? By Kiran Vittal Tags: Debug, Prototyping, Chip Design Insights, Emulation, Verification, Virtual Prototyping, Formal Verification
BLOG 5 min read/Oct 06, 2021 BLOG RTL Debugging via FPGA Prototyping: SoC Design Challenges? By Rob Parris Tags: Debug, Prototyping, Chip Design Insights, Verification
BLOG 5 min read/Sep 20, 2021 BLOG Upgrading FPGA Prototyping for RTL Debug Productivity By Rob Parris Tags: Debug, Prototyping, Chip Design Insights, Verification
BLOG 5 min read/Feb 23, 2021 BLOG Verifying Complex Datapath Designs with HECTOR? By Kiran Vittal, Alfred Koelbl, Pratik Mahajan Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification