Cloud native EDA tools & pre-optimized hardware platforms
草榴社区 PrimeShield? solution provides design robustness analysis and optimization at advanced nodes and enables designers to effectively improve design robustness in face of escalating process and voltage variability. It enables designers to reduce design power and boost frequency by minimizing over-pessimism, over-margin and over-design while ensuring design safety.
草榴社区 PrimeShield can rapidly identify and drive optimization of bottlenecks at the stage, path and design level that are sensitive to variations such as supply voltage drops or manufacturing variability. The patented fast statistical methods and breakthrough machine learning technology are used to firmly establish design robustness analysis as a method to minimize failure and maximize power, performance and area (PPA). 草榴社区 PrimeShield delivers 100X-10,000X faster design robustness analysis and optimization than existing solutions. It is scalable to volume production system- on-chips (SoCs) with billions of transistors, while using industry standard inputs for immediate deployment.
Identifies and optimizes critical bottleneck cells delivering improved design robustness
ML-Fast Monte Carlo methods minimizes failures, delivers up to 10,000X faster HSPICE accurate for high-sigma/automotive applications
Reduces pessimistic timing margins to recover and maximize PPA for High-Performance & Low-Power designs
As part of the Digital Design Family, 草榴社区 PrimeShield delivers silicon designs that are faster, lower power, more robust and more cost-effective.
草榴社区 PrimeShield's innovative fast statistical engine uniquely leverages the core engines of the industry’s gold-standard 草榴社区 PrimeTime? signoff and 草榴社区 HSPICE? simulation tools. It overcomes the turnaround time challenges that previously prohibited full statistical design variation analysis with machine learning technologies, enabling analysis and optimization for every design of any size.
Accelerated by machine learning technology, the 草榴社区 PrimeShield solution performs fast Monte Carlo statistical simulation on critical timing paths with HSPICE accuracy within minutes, versus days or weeks required by full statistical simulations. Its patented design variation analysis with statistical correlation modeling enables analysis and optimization on large-scale SoCs with billions of cells, an analysis previously feasible only for a few dozen cells.
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