Cloud native EDA tools & pre-optimized hardware platforms
ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries. It is used to ensure that two design representations are functionally equivalent. These designs may be represented as Verilog behavioral model, RTL, Gate, Switch or SPICE or .db netlist views.
Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker
Register NowLeveraging Symbolic Simulations For IO Verification
Cell Library Verification Using Symbolic Simulation
Detecting Electrical Hazards Incurred By Inter-Voltage Domain Crossing In Custom SRAMs
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