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The ²ÝÁñÉçÇø 224G Ethernet PHY IP, an integral part of ²ÝÁñÉçÇø¡¯ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the ²ÝÁñÉçÇø 224G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications.

The area efficient PHY demonstrates zero post-FEC BER with ultra-high power efficiency for upcoming OSFP and OSFP -XD form factors. The 1.25-224Gbps PHY supports Pulse-Amplitude Modulation 4 and Non-Return-to-Zero (NRZ) signaling to deliver up to 1.6T Ethernet in an eight lane configuration.

The configurable transmitter and advanced DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance.

The PHY integrates with the ²ÝÁñÉçÇø Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.

Combined with ²ÝÁñÉçÇø¡¯ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, ²ÝÁñÉçÇø provides a comprehensive 224G Ethernet PHY solution for fast and reliable SoC integration.

²ÝÁñÉçÇø 224G Ethernet PHY IP