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The ²ÝÁñÉçÇø Die-to-Die Controller IP, optimized for latency, bandwidth, power, and area, enables efficient inter-die connectivity in server, AI accelerator, networking, and high-performance computing SoCs. The controller interoperates with the ²ÝÁñÉçÇø 112G XSR PHY to deliver a complete Die-to-Die solution for a seamless connection between the on-die interconnect fabrics in both dies via the standard CXS port. The ²ÝÁñÉçÇø Die-to-Die Controller uses a FLIT-based architecture to minimize latency. It implements an advanced error detection and correction mechanism including Cyclic Redundancy Check (CRC) and optional latency-optimized Forward Error Correction (FEC) to reduce Bit Error Rate (BER) to a very low level for PAM-4 or NRZ PHY signaling. The embedded retry protocol enables very low latency, error-free links between two dies.

The ²ÝÁñÉçÇø Die-to-Die Controller optimizes system performance by supporting two configurations for coherent and non-coherent data traffic between the SoC bus and each die. The latency-optimized configuration interfaces with the SoC fabric via a FLIT-based interface (Arm? CXS). The ²ÝÁñÉçÇø Die-to-Die Controller can be extended to support any aggregate bandwidth between the two dies using bifurcation into multiple parallel links.

Additional resources:
Glossary page: What is a Die-to-Die Interface?
Blog:

²ÝÁñÉçÇø Die-to-Die Controller IP