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The ²ÝÁñÉçÇø XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The low-latency, low-power, and compact PHY supports NRZ and PAM-4 signaling from 2.5G to 112G data rates and is compliant with the OIF CEI-112G and CEI-56G standards for extra-short reach (XSR) links. The XSR PHY offers a flexible layout for maximum bandwidth per die edge by allowing the placement of the square macros along all edges of the die. It deploys 16-lane transmit and receive macros for optimized segmentation on the multiple dies. The robust DLL-based clock-forwarded architecture enables high energy efficiency while supporting reliable links of up to 50 millimeters for large MCMs. The PHY enables multi-die connectivity over organic substrates, which helps reduce packaging costs without requiring advanced interposer-based packaging over shorter distances. The embedded bit error rate (BER) tester and nondestructive 2D eye monitor capability provide on-chip testability and visibility into channel performance. Besides the PMA and PMD, the PHY includes a raw PCS to facilitate the interface with the on-chip network, regardless of the existing networking protocol. The XSR IP is combined with ²ÝÁñÉçÇø¡¯ comprehensive routing feasibility analysis, package substrate guidelines, signal and power integrity models, and crosstalk analysis for fast and reliable integration into SoCs.

Additional resources:
Glossary page: What is a Die-to-Die Interface?
Blog:

²ÝÁñÉçÇø XSR PHY IP