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Whether you are switching from app to app on your smartphone or enjoying an immersive gaming experience, you would notice sluggish memory access speeds on these systems. More critically, if your car¡¯s autonomous braking system did not respond quickly to an obstruction on the road ahead, you would undoubtedly be concerned.

Today¡¯s smart, connected, and bandwidth-intensive applications rely on blazingly fast, low-latency memory access to deliver an array of functions we rely on every day. The conduit making all this possible? The LPDDR5X SDRAM JEDEC standard, an optional extension to LPDDR5.  

Published by JEDEC in June 2021, the LPDDR5X standard, a dedicated type of synchronous dynamic random-access memory (SDRAM), delivers enhancements in several areas compared to the preceding LPDDR5 standard:

• A speed increase from 6.4Gbps to 8.5Gbps using the same 1.1V core voltage.
• Better signal integrity enabled via receiver equalization and transmitter pre-emphasis.
• Greater reliability thanks to a new adaptive refresh management feature.
• Up to 20% better battery efficiency.

All of this is welcome news for the 5G mobile world as well as AI, automotive, and even some high-performance computing applications. Chips integrating LPDDR5X interfaces and developed on advanced process nodes further extend the bandwidth and power efficiency benefits. Read on to learn more about applications ideally suited for LPDDR5X and how silicon-proven IP can help optimize designs. 

LPDDR5X Specification: Robust Speed Without the Power Penalty

LPDDR (low-power double data rate) memory was developed to address the needs of increasingly popular smartphones and other mobile communication electronics. To meet consumer demands as well as the limitations of their small form factors, these devices need ways to maximize battery life, which LPDDR provides. The memory standard is now just as commonly used as its predecessor, DDR, thanks to a combination of bandwidth, power efficiency, form factor, and capacity that makes it the ¡°just right¡± SDRAM for a wide range of end applications.

The advantage of LPDDR is that it is very good at dissipating very little power when the memory isn¡¯t needed by the end device. Compared to DDR, the low-power standard makes it easy to quickly throttle performance up and down, as it operates at a lower frequency. By going into a low-power state when the end device isn¡¯t being used, LPDDR enables significant power savings. LPDDR5X is the fastest and most efficient version of the standard yet.

A variety of applications and end devices need fast memory access for real-time decisions:

• Smartphones and other mobile applications that require high bandwidth and optimized power consumption with the ability to change frequencies based on device activity.
• Automotive processors supporting applications such as advanced driver assistance systems (ADAS). Most automotive applications use automotive-grade SDRAMs that meet more stringent standards compared to the traditional consumer grade of product.
• AI accelerators, which are high-performance parallel computation machines that enable efficient processing of AI workloads like neural networks.
• Edge AI, where data needs to be processed quickly and locally with zero latency.
• Chips for camera and video devices, digital home products like TVs and routers, and media equipment, which must perform quick ultra-high-density (UHD) multimedia processing.
• 5G networking equipment, which requires real-time data transfer to support fast data downloads and uploads. 

Optimizing PPA on Advanced Processes

Advanced process technologies provide ways to generate greater power, performance, and area (PPA) advantages for advanced system-on-chips (SoCs). Chip architectures on the most advanced FinFET nodes contain billions of transistors in small, dense silicon packages, creating new challenges along the path to volume production. Memory interface IP can help streamline the development process, providing silicon-proven solutions that mitigate integration risks and accelerate overall time to market. 

For LPDDR5X, the physical layer (PHY) and controller work hand-in-hand to support low-latency operations and fast data transfers with optimal power efficiency. As an active member of the JEDEC Solid State Technology Association¡¯s subcommittee for low-power memories, ²ÝÁñÉçÇø experts help shape the LPDDR memory interface standard as it evolves. Our portfolio includes robust LPDDR5X PHY and controller IP with the lowest latency and area for the latest standards. ²ÝÁñÉçÇø LPDDR5 Controller IP includes an integrated Inline and Memory Encryption (IME) Security Module, ensuring data confidentiality with standards-compliant independent cryptographic support for read/write channels and per region encryption/decryption. The controller is highly optimized for the lowest latency, area, and performance.

²ÝÁñÉçÇø LPDDR5X/5/4X PHY IP is suited for ASICs, ASSPs, SoCs, and system-in-package applications and available with flexible configuration options. It is designed to rapidly integrate with ²ÝÁñÉçÇø LPDDR5X/5/4X Controller IP, which is optimized for power, latency, bandwidth, and area, for a complete DDR interface solution. The LPDDR5X PHY IP on the semiconductor industry¡¯s most advanced FinFET process technologies down to 3nm has demonstrated blistering speeds (8533Mbps and up to 9600 Mbps ¨C overclocked!) with wide open eyes and clear margins.

Watch our test chip demo video to see the PHY IP in action:

By working with an established IP supplier, designers can proceed with confidence that our IP is thoroughly tested under different operating conditions, including extreme temperatures and scenarios involving electromigration, as well as qualified to certain standards (such as functional safety for automotive).