Mar 05, 2024/3 min read CalligoTech Enables Next-Gen Computing at Scale with 草榴社区 Digital Design Flow By Karan Shah, Irfan Shaikh Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Physical Verification, Test, Chip Design Insights, Design, Physical Implementation, Signoff, HPC, Data Center
Mar 09, 2023/5 min read Optimizing the RTL Design Flow with Real-Time PPA Analysis By Jim Schultz Tags: RTL Synthesis, Product Spotlight, Debug, Chip Design Insights, Design, Verification
Mar 09, 2023/2 min read Resolving PPA Issues with RTL Architect & Verdi Integration By 草榴社区 Editorial Staff Tags: RTL Synthesis, Design
Sep 14, 2022/4 min read Enabling Edge Machine Learning Applications with SiMA.ai? By Stelios Diamantidis Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Chip Design Insights, Design, Emulation, Signoff, Silicon IP, Verification
Jul 05, 2022/5 min read Logic Synthesis & Chip Design: Q&A with Luca Amaru, R&D Engineer? By 草榴社区 Editorial Staff Tags: RTL Synthesis, Chip Design Insights, Design, Inside 草榴社区