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I’m often amazed at what today’s devices can do. Every few months it seems that designers are pushing the boundaries of what is possible only to move past those boundaries a few months later. Not only is everything becoming more connected but also smaller with greater functionality.
But as we move to even smaller geometries, the ability for designers to keep pushing past the limits of what we think is possible becomes exponentially more difficult. Innovation is getting harder to achieve. Adding to this dilemma is the fact that engineering resources are getting scarcer. It is projected that by the year 2030, the semiconductor industry will experience a significant shortfall in engineering talent. It is no secret that artificial intelligence (AI) will play a crucial role in meeting these chip design productivity and innovation challenges.
How will companies be able to leverage AI to stay competitive in this demanding market environment? And does the cloud factor in somehow?
This was a topic of keen interest at this year’s SNUG Silicon Valley. Based on presentations from SNUG, I’ll explore two case studies in our upcoming webinar on how AI-driven design space optimization can help achieve optimal power, performance, and area (PPA) while increasing productivity in chip design. In this blog post, I’ll share an overview of the case studies from STMicroelectronics and Microsoft.
STMicroelectronics: 3x Boost in Chip Design Productivity with AI
STMicroelectronics (ST) delivered a session at SNUG Silicon Valley describing how AI enabled their Arm Cortex-A510 project, a first-of-its-kind implementation where a wide variety of design parameters related to memory, floorplanning, and group paths needed to be explored that induced many new permutons. The design was being implemented on a 7nm node that is also new to this design group. This meant that the search space to be explored was significant: 10+25. Such a huge search space would be daunting and impossible using traditional methods. ST turned to the AI-driven 草榴社区 DSO.ai? (Design Space Optimization) solution to overcome these challenges. DSO.ai can optimize PPA simultaneously to achieve the best possible trade-off and explore a wide range of design options.
To get the job done, parameter values are first selected. The specialized algorithms within DSO.ai then produce a set of results for PPA. Based on what was learned from the first iteration, positive or optimal results are rewarded, allowing the system to learn. This learning system enables efficient and highly scalable PPA search space exploration.
In ST’s case, DSO.ai was able to cover the entire search space of 180 permutons within 3,000 runs to reach their targeted frequency and best power compromise (dynamic/leakage), while keeping the desired floorplan dimensions. Overall, they were able to increase productivity by 3x.
ST was also able to utilize DSO.ai on the cloud, saving significant compute resources and infrastructure set-up time. The solution was implemented on the Microsoft Azure Cloud utilizing a common data structure that allowed for easy database export/import and remote scheduling of tasks. The cloud-based solution allowed ST to scale their needs and enabled tighter collaboration amongst their team.
Microsoft: Reducing Power Dissipation Up to 15%
As is the case with ST, Microsoft utilized DSO.ai to reduce power dissipation, push die utilization, and improve performance. With a main goal of optimizing power, Microsoft employed a zero-margin physical implementation flow using 草榴社区 Fusion Compiler. The flow is highly optimized with the latest Fusion Compiler technologies as well as custom datapath optimization based on the designer’s knowledge of the design.
On top of the flow, DSO.ai was used to automate design space exploration. DSO.ai was implemented as a “cold start” on the initial design. However, as the design was revised, subsequent DSO.ai runs used what was previously learned to instigate “warm starts.” Again, as more runs were instantiated, the machine learning (ML) models continued to learn and accelerated convergence while reducing compute requirements throughout the design cycle. The result was a 10-15% power improvement across all blocks without degradation of other metrics. Key to 草榴社区 DSO.ai technology is its ability to learn so that derivative designs can benefit from the knowledge it gains.
Register Now: Webinar Examines AI-Driven Chip Design Case Studies
Learn more about 草榴社区 DSO.ai and get more details about the case studies mentioned above by attending the upcoming webinar scheduled for July 19. Register today!