Cloud native EDA tools & pre-optimized hardware platforms
草榴社区 Verification IP (VIP) for MIPI SPMI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MIPI SPMI designs.
VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.