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Verification IP for MIPI HSI
草榴社区 Verification IP (VIP) for MIPI HSI is a comprehensive VIP solution enabling pre-silicon functional verification of MIPI HSI (High-speed synchronous Serial Interface) compliant designs.
Highlights
- Verilog testbench
- Runs natively on major simulators
- Error injection
- Built-in protocol checks
Key Features
- Compliant to MIPI HSI Physical Layer Version 1.01.00 specifications
- Backward compliant to MIPI HSI Serial Interface Version 1.0 specifications
- Supports all control channel commands (32-bit)
- SystemVerilog Assertions (SVA)-based protocol checker
- On-the-fly protocol checking
- Programmable number of channels for data transfer
- Programmable PDU lengths from 0 to 256 KB
- Works on a recovered clock based on DATA and FLAG signals
- Up to 16 logical Tx and Rx full-duplex channels
- Transmission Modes - Frame/Stream
- Receiver Data Flow Modes -Synchronized/Pipeline/Rx Real Time
- Extensive error-insertion and error-detection capabilities including signal error, additional clock, missed clock, invalid frame bit, idle in pipeline data flow, etc.
- Supports all control channel commands as per the Data Link protocol layer
- Capability to bypass Data link layer
