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Verification IP for MIPI SoundWire
草榴社区 Verification IP (VIP) for MIPI SoundWire provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of MIPI SoundWire devices operating with basic and High-PHY links. VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with built-in verification plans, example tests, and functional coverage. VIP is natively integrated with Verdi? Protocol Analyzer, a protocol centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.
Highlights
- Native SystemVerilog/UVM
- Optional source code test suite
- Runs natively on all major simulators
- Verification plan and coverage
- Built-in protocol checks
- Verdi protocol-aware debug
- Error injection
Key Features
- MIPI SoundWire 1.2
- MIPI SoundWire 1.1 specification
- Interfaces
- DDR/NRZI signaling
- Multi-Lane support
- Internal/external clocking
- Synchronization and Enumeration
- Normal and Flow Control payload transport
- Bank switching
- Resets and Interrupts
- Test Data Modes and Clock Stop Mode
- High-PHY
- Dynamic number of Slaves
- Bulk payload transport
- Extensive callbacks and messaging
- Configurable data ports
- Power-on reset
- SoundWire Device Class for Audio Register Controls (SDCA)
- Commit Mechanism for Dual Ranked Registers
- Atomic Access Mechanism for Multi-byte Quantities
- Bus Clock Speed Encoding
Test Suites
The Test Suite for MIPI SoundWire is a complete self-contained, configurable environment targeted at the verification of MIPI SoundWire designs. It is provided as SystemVerilog UVM source code to simplify integration, enable user customization and maximize reuse across projects. The MIPI SoundWire test suite incorporates 草榴社区’ technology leading native SystemVerilog VIP for MIPI SoundWire.