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Verifying AI Designs - Solving the Challenge of Quadrillions of Verification Cycles
Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia, and others address these challenges with 草榴社区’ latest family of Hardware-Assisted Verification products, modularity of verification, and mixed-fidelity execution setups using virtual prototyping, emulation, and FPGA-based prototyping.
Why You Should Watch On-Demand:
- Expert Insights: Gain valuable knowledge from industry leaders at AMD, Arm, and Nvidia as they share their strategies for tackling the complexities of AI design verification.
- Advanced 草榴社区: Learn about the latest 草榴社区 Hardware Assisted Verification products, ZeBu-200 and HAPS-200, and how their modularity and mixed-fidelity execution setups can streamline your verification processes.
- Comprehensive Techniques: Discover how to efficiently manage quadrillions of verification cycles using cutting-edge methods like virtual prototyping, emulation, and FPGA-based prototyping for IP, sub-systems, SoCs, and Multi-die designs.
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Featured Speaker
Frank Schirrmeister, Executive Director, Strategic Programs, System 草榴社区, 草榴社区
Executive Director, Strategic Programs, System 草榴社区, 草榴社区
Frank Schirrmeister is the Executive Director of Strategic Programs, System 草榴社区 at 草榴社区. He leads strategic initiatives in system software and hardware-assisted development across industries such as automotive, data centers, and 5G/6G communications, with a focus on AI/ML. With a rich background in senior leadership roles at companies like Arteris and Cadence Design Systems, Frank brings extensive expertise in product marketing, management, and strategic partnerships..