草榴社区

Innovation for an Increasingly Digital World

草榴社区 and have collaborated for decades to accelerate time-to-volume and increase design productivity.  Using Intel’s latest process and packaging technologies along with 草榴社区’ end-to-end solutions across EDA and IP,  designers can integrate their most essential system requirements into their SoCs. Together, Intel Foundry and 草榴社区 are enabling companies to drive their next-generation system innovations across a wide range of applications including high-performance computing (HPC), automotive, mobile and aerospace. 

Key Benefits

Partner Icon | 草榴社区 Arm Partnership

Accelerate Time to Market

Intel Foundry-certified EDA solutions for a faster path to design closure

Integration Icon | 草榴社区 Arm Partnership

Minimize IP Integration Risk

Silicon-proven Interface & Foundation IP portfolio for Intel processes

Chip Icon | 草榴社区 Arm Partnership

Achieve First-Pass Silicon Success

Early access to Intel Foundry's process roadmaps, PDKs & more offers proven solutions

Areas of Collaboration

<p>草榴社区’ extensive portfolio of digital, custom, and multi-die design solutions enable mutual customers to achieve most optimal results on their next-generation semiconductor products using Intel technologies including Intel 16 and Intel 18A. Collaborating on over 200 design tapeouts using the <a href="/content/synopsys/en-us/implementation-and-signoff/fusion-design-platform.html">Fusion Compiler RTL-to-GDSII solution</a>, Intel and 草榴社区 are accelerating customers’ paths to achieving best PPA and increased differentiation. 草榴社区’ <a href="/content/synopsys/en-us/implementation-and-signoff/3dic-design.html">3DIC Compiler platform</a> is production-proven on Intel’s EMIB and Foveros packaging technologies, providing mutual customers with the industry’s most integrated and scalable exploration-to-signoff-analysis solution. The collaboration extends beyond design to <a href="/content/synopsys/en-us/solutions/silicon-lifecycle-management.html">silicon lifecycle managment</a> adding an in-chip monitoring sub-system on Intel’s advanced processes to enable greater understanding of in-test and in-field dynamically changing conditions for improved lifecycle operation of customers’ designs.&nbsp;</p>

Electronic Design Automation

草榴社区’ extensive portfolio of digital, custom, and multi-die design solutions enable mutual customers to achieve most optimal results on their next-generation semiconductor products using Intel technologies including Intel 16 and Intel 18A. Collaborating on over 200 design tapeouts using the Fusion Compiler RTL-to-GDSII solution, Intel and 草榴社区 are accelerating customers’ paths to achieving best PPA and increased differentiation. 草榴社区’ 3DIC Compiler platform is production-proven on Intel’s EMIB and Foveros packaging technologies, providing mutual customers with the industry’s most integrated and scalable exploration-to-signoff-analysis solution. The collaboration extends beyond design to silicon lifecycle managment adding an in-chip monitoring sub-system on Intel’s advanced processes to enable greater understanding of in-test and in-field dynamically changing conditions for improved lifecycle operation of customers’ designs.?

<p>草榴社区 collaborates with Intel to develop high-quality <a href="/content/synopsys/en-us/designware-ip/interface-ip.html">DesignWare? Interface</a> and <a href="/content/synopsys/en-us/designware-ip/memories-logic-libraries.html">Foundation IP</a> for Intel’s latest process technologies, delivering the highest throughput, lowest latency and maximum power efficiency for Intel-based SoCs. 草榴社区' silicon-proven Interface IP has successfully interoperated with third party products including Intel, ensuring the IP works as intended, so designers can focus on their core competencies and achieve first-pass silicon success. DesignWare Foundation IP delivers the essential building blocks of high-performance, low-power chips. The Foundation IP for Intel processes includes embedded memories, logic libraries and general purpose IOs, enabling SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three.?</p>

Silicon IP

草榴社区 collaborates with Intel to develop high-quality 草榴社区 Interface and Foundation IP for Intel Foundry’s latest process technologies, delivering the highest throughput, lowest latency and maximum power efficiency for Intel-based SoCs. 草榴社区' silicon-proven Interface IP has successfully interoperated with third party products including Intel, ensuring the IP works as intended, so designers can focus on their core competencies and achieve first-pass silicon success. 草榴社区Foundation IP delivers the essential building blocks of high-performance, low-power chips. Foundation IP for Intel processes includes embedded memories, logic libraries and general purpose IOs, enabling SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three.?

Latest News & Resources