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Distributed data processing in ICs need high speed data transfer between the ICs. Parallel and serial are the two options to transfer data between chips. Parallel data transfer requires multiple connections between ICs compared to serial data transfer that only needs one pair of connection.

SerDes is the most fundamental building block of a physical layer for chip-to-chip interconnect systems:

SerDes + Physical Coding Sublayer (PCS) = PHY or Physical Layer

The Open Systems Interconnection (OSI) model defines physical layer, or PHY, as an abstraction layer responsible for transmission and reception of the data. It is the lowest layer in the OSI model, which also includes: 

• Application layer
• Presentation layer
• Session layer
• Transport layer
• Network layer
• Datalink layer

Different protocols suggest various abstraction division for a PHY. For example, 100G PHY defined by IEEE 802.3 has the following abstraction layers:

²ÝÁñÉçÇø is a leading provider of high-quality, silicon-proven IP solutions for SoC designs implemented in today¡¯s most widely adopted devices and systems across a wide range of markets including: 

• Mobile
• Automotive
• Cloud computing 
• High-performance computing (HPC)
• Artificial intelligence (AI)
• Internet-of-things (IoT)
• 5G

²ÝÁñÉçÇø' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.

• 224G Ethernet PHY IP and 112G Ethernet PHY IP enable true long reach channels for up to 800G/1.6T high-performance computing SoCs
• 56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications
• Die-to-Die PHY IP for UCIe and 112G XSR
• Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols
• PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 128GT/s SoCs on advanced FinFET processes