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Definition
Silicon Lifecycle Management (SLM) is an emerging paradigm associated with improving silicon health through the monitoring, analysis and optimization of semiconductor devices as they are designed, manufactured, tested and deployed in end user systems. Increasing chip and system complexities combined with growing performance and reliability requirements are driving the need for on-going maintenance and optimization of semiconductor devices throughout their entire lifecycle.
SLM is based on two underlying principles:
- Deploying monitors and structures embedded within silicon designs to gain insight on how devices are made and how they then perform in-field
- Gathering and analyzing data at every opportunity throughout the lifecycle of silicon devices to provide powerful analytics that enable in-design, in-test and in-field observations and device improvements to be made
The first principle is achieved by expanding upon the data already available from test and product engineering with deep visibility into each chip’s operation through monitors that are embedded throughout each chip and measure targeted activities across a wide set of contexts and conditions. Targeted analytics on this chip data enable optimizations at each stage of the semiconductor lifecycle, starting from the in-design, in-ramp and in-production phases and culminating with in-field operation.
How Does Silicon Lifecycle Management Work?
Detailed measurements from the chip on all aspects of its operation are needed to obtain the knowledge required for effective analysis and decision-making during the silicon lifecycle process. Sources of this data include environmental process/voltage/temperature (PVT) monitors, design for test (DFT) and built-in self-test (BIST) resources, structural monitors for path margin analysis and functional monitors to measure clock delay and other activities, The data from the monitors is then transported off chip and stored in a unified SLM database ready to be analysed. Based on this analysis, insightful decisions can then be made and action taken.
Combining silicon operational data extracted during each lifecycle stage adds an extra dimension to the data richness. Targeted analytics are performed at each lifecycle stage to drive optimizations specific to each phase. The expanded knowledge base greatly enhances the analytics and optimizations possible at each lifecycle stage.
What are the Benefits of Silicon Lifecycle Management?
Silicon lifecycle management delivers multiple benefits to the chip designer and the end user of that chip. These include enhanced chip performance, smoother and faster product bring-up and enhanced performance and security over the life of the chip. Specific benefits include:
- Improved silicon health
- Increased design performance
- Faster product yield ramp and improved product quality
- Accurate failure analysis
- Test time reduction and improved product quality
- Faster time-to-market for chips and systems
- Performance, power, reliability and security optimized throughout operational life
Improved Design Performance
Silicon data extracted during manufacturing test is used to calibrate design modelling parameters. Data from ring oscillator measurements, critical path test results and PVT monitors, path margin monitors and clock delay monitors are all example sources of this data.
Through a series of data mining, correlation and root cause analysis, the robustness and accuracy of the models used in chip design is improved. This allows initial chip design to converge on an optimal result faster.
Faster Product Yield Ramp and Improved Final Yield
This process correlates silicon data with physical design data to identify systematic yield limiting issues. The sources of the silicon data include test failure diagnostic data, process/voltage/temperature (PVT) monitor data and structural data.
Through a series of data mining, correlation and root cause analysis steps dominant yield loss mechanisms can be identified. This allows acceleration of the “yield learning” process to optimize the final product yield.
Test Time Reduction and Improved Product Quality
Synergies between the 草榴社区 Test and Silicon Lifecycle Management (SLM) product families ensure the highest quality, lowest cost test and optimal silicon health for your device. Integrated tools, IP and methodologies provide actionable insights by testing, monitoring and analyzing at every phase of the device lifecycle. The unified solution delivers enhanced performance, eases implementation and minimizes impact on design PPA.
SLM adapts test and screening criteria through ongoing analysis of silicon and manufacturing test result data. Optimized test criteria will reduce test time and ensure only good devices are released to production.
Sources of this data include manufacturing test results, process/voltage/temperature (PVT) monitor data and structural monitor data. Through a process of data mining, monitoring/analysis and reporting, adaptive test alerts and enhanced control measures can be implemented. The ability to detect outliers, or chips that exhibit performance outside of normal limits, is also enhanced.
The result is reduced test time and improved quality of the delivered chip.
Faster Time-to-Market for Chips and Systems
In any complex chip, there are interactions between hierarchical interconnects, heterogeneous processors, various operating systems and bare metal software. All these interactions must be harmonized in order get the chip and the system that uses it to market. Adding to this challenge is the fact that most systems are designed without really knowing what the workload will look like when the final system is deployed.
SLM can address these challenges through deep insight into the functionality of the compute, communication and storage resources on a chip. The combination of functional and structural monitors embedded in the chip, together with analysis software enable much faster and deeper understanding of the behavior of the chip’s operation and how it interacts with the overall system. In addition, during the life of the system, workloads change, software and firmware requirements change and transistors age. SLM also provides insights to allow the chip and system to adapt to these changes. The result is shorter development time, improved validation efficiency and better long-term performance.
Performance, Power, Reliability and Security Optimized Throughout Operational Life
The performance of a silicon chip does not remain constant over its operating life. Aging effects in the silicon structures change the performance characteristics of the device over time. The system operating environment can also contribute to changes in chip performance. These effects include environmental temperature effects, process variation, voltage supply fluctuation and the impact of changes in workload and electrical operating parameters. Security breaches can also impact chip performance.
Semiconductor devices are performing more mission critical and safety-related functions in systems today. This makes the robustness and reliability of these devices more important. Many of these systems have a long operating life, and time also contributes to the gradual change in performance of semiconductor devices.
Silicon lifecycle management provides a data collection, analysis and control environment to monitor all of these effects and implement corrective actions in the field at a unit device level. The result is far more stable and secure performance of the silicon device and overall system over time.
What 草榴社区 Does 草榴社区 Offer?
The 草榴社区 Silicon Lifecycle Management Family includes multiple integrated products and capabilities. The key components of this end-to-end solution are highlighted below:
- 草榴社区 SLM environmental, structural and functional monitoring IP combined with existing (DFT) and built-in self-test (BIST) resources provides the rich set of silicon data which forms the foundation of the Silicon Lifecycle process
- 草榴社区 TestMAX? and the 草榴社区 Digital Design Family RTL-to-GDSII solution provide automated integration of the 草榴社区 SLM Platform monitors and analytics tools into the RTL or gate-level design
- The 草榴社区 SLM Family links 草榴社区 TestMAX to the golden signoff solution Fusion Digital Design Family for guidance on optimal placement of the 草榴社区 SLM embedded monitors
- 草榴社区 Digital Design Family closes the loop on design implementation by leveraging silicon data-based timing model calibration to minimize required margins as well as advanced analytics to further optimize design power, performance and area (PPA), reliability and silicon predictability
- 草榴社区 High-Speed Access & Test (HSAT) IP provides adaptive high bandwidth testing over functional interface as well as high speed access to DFT & Silicon monitoring network through entire Silicon Lifecycle
- 草榴社区 TestMAX? ALE enables an extremely high, test bandwidth for die testing to in-system test and on to all stages of the product lifecycle
- 草榴社区 Optimizer provides performance optimization software to improve compute system performance, automatically and in real-time
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