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With huge demands for data compute, allowing more processing in a tiny area at low power is a must. By contrast, for 2D designs, more processing means an increase in chip area and power. 3D designs, or vertical integration, have emerged as a viable solution. A 3DIC architecture increases functional density at the same or reduced power, keeping the same or smaller area. This results in a smaller package for electronic devices. 

In 2D ICs, each die is packaged separately and laid out on a printed circuit board (PCB). Multiple dies in the same packages are then connected using conductive wire paths. Stacking multiple dies atop each other in a single package takes less space than if those dies were placed side by side. Shorter distance between stacked dies allows faster data exchange from one known good die to another, using less energy.

Data transfer to and from stacked dies takes place through TSVs integrated in the bottom die. These TSVs are physical pillars running vertically made up of conductive material such as copper. Bonding stacked dies into a single package instead of a multiple package on a PCB increases I/O density by 100x. The energy-per-bit transfer can be reduced to 30x with the latest technology.  

With the slowing of Moore’s law, packing more functionality into a single die is not always the best way to develop the next generation of semiconductor devices. 3DICs offer a viable and valuable alternative, delivering at performance, power, and footprint benefits through the vertical stacking of silicon wafers or dies into a singly packaged device. Benefits include:

• Reduced Cost and Footprint. Increasing design sizes (both in terms of functionality and densities) are causing major cost and yield problems and expanding development cycles. From a cost perspective, a large system with different parts has various sweet spots in terms of silicon implementation. Rather than having the entire chip at the most complex and/or expensive technology node, heterogeneous integration allows the use of the ‘right’ node for different parts of the system. This reserves the use of advanced/expensive nodes for only the critical parts of the system and less expensive nodes for the less critical parts.
• Higher Bandwidth. When you think of large, complex SoC, typically the first optimization considered is area. Silicon designers want to integrate as much functionality into the chip and deliver as high performance as possible. But then there are always the required power and thermal envelopes, particularly critical in applications such as mobile, wearable AR, and IoT (although also increasingly important in areas such as high-performance computing in a data center when overall energy consumption is prioritized as well). Implementing 3D structures enables designers to continue to add functionality to the product, without exceeding the footprint and height constraints and, at the same time, lowering silicon costs.
• Lower Power Consumption. As the need for lower power consumption surges, smaller package sizes have been increasing in demand. 3DICs can yield a solution with greater capacity (gates and memory) that could possibly fit on one die in the most advanced technology node available. Vertical stacking provides shorter, faster interconnects that reduce power consumption.
• Heterogeneous Integration. Using multiple heterogeneous dies provides flexibility, since different manufacturing processes, technology nodes and even base technologies can be intermixed. Existing chips can be reused without being redesigned for incorporation into a single die, another form of risk reduction. In addition, it provides the opportunity to target multiple end-market applications through reuse.

3DICs are ideal for all kind of chips that target more transistors, less power, or small area. A multitude of different chip segments have different advantages from using 3DIC technology and 3DICs are finding increasing acceptance in some of the most demanding semiconductor applications.

The compact footprint is valuable for mobile devices, internet of things (IoT) and other applications where space is at a premium. The capacity and flexibility are ideal for compute-intensive applications such as high-performance computing (HPC), data centers, cloud computing, artificial intelligence (AI), and machine learning (ML).

The chart below shows the growing segments benefitting from 3DIC technology:

3DIC Compiler

草榴社区 3DIC Compiler is the electronic design automation (EDA) industry’s only unified platform for end-to-end multi-die design and integration within one package. It provides a single graphical user environment with 3D visualization, supporting the exploration, design, implementation, validation, and signoff of 3DICs. It is built on the 草榴社区 Fusion Design Platform? SoC-scale IC design common data model, providing scalability in capacity and performance. 3DIC Compiler enables hundreds of thousands of inter-die interconnects, which traditional IC packaging tools cannot deliver. It offers a full set of automated features along with power integrity, as well as thermal and noise-aware optimization that minimizes the number of design iterations.

Benefits of this technology include:

• A holistic approach to multi-die integration, for an optimal system-in-a-package solution
• Powerful 3D viewing of the unified platform, providing an intuitive environment and shortening overall integration time
• Seamless integration of Ansys’ silicon-package-PCB technology for system-level signal integrity, power integrity and thermal analysis, enabling faster convergence and reducing the need for iterations

DesignWare IP

Designers are splitting SoCs into multiple dies to improve yield, PPA, and scalability for various use cases such as die splitting, die disaggregation, compute scaling and aggregation of functions. To meet the extensive die and SDRAM connectivity requirements for such multi-die SoCs, designers are using 草榴社区’ silicon-proven DesignWare Die-to-Die and HBM IP solutions. The solutions offer low-latency controllers and power-efficient PHYs available on the most advanced FinFET processes, supporting 2.5D or 3D packaging technologies. The die-to-die IP enables reliable 112G XSR and parallel-based HBI links, and the HBM IP allows up to 921 GB/s HBM3 SDRAMs.