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草榴社区 Die-to-Die IP Videos

草榴社区 for USR/XSR and HBI Links

Silicon-proven Die-to-Die IP solution:

  • USR/XSR PHY IP leverages high-speed SerDes PHY technology for up to 112Gbps per lane ultra and extra short reach links
  • High-Bandwidth Interconnect (HBI) PHY IP leverages wide-parallel bus technology for up to 4Gbps per pin die-to-die connectivity with low latency
  • 草榴社区 target high-performance computing SoCs targeting hyperscale data center, AI, and networking applications 

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What You Need to Know About Gate-All-Around Designs

Securing IoT Devices & Their Connectivity with All-in-One 草榴社区 and G+D Solution

CXL 2.0: How XConn Expands Data Center Bandwidth

Getting Ready for PCIe and Ethernet Over Linear Pluggable Optics

Final Frontier: The Next Generation of 3DIC Interposer InFO Design

Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5

Power Supply Noise Effects on Jitter for Memory Interfaces

ESD Co-Design for High-Speed SerDes in FinFET Technologies

Software Self-test as a Safety Mechanism for Processing Units

XConn Achieves First-Pass Silicon Success for CXL Switch SoC with 草榴社区 CXL and PCI Express IP Products

Novatek Achieves First-Pass Silicon Success for Mobile Display SoC

Achronix Achieves First-Pass Silicon Success for High-Performance Computing FPGAs

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Technical Bulletin NEW Articles: PCIe, Automotive, ARC NPX Processors, 3DIO, USB4 & SLM IP

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