Cloud native EDA tools & pre-optimized hardware platforms
草榴社区 Webinar
Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb of repair information to meet yield requirements. Designers are facing the challenges of creating secure, reliable, and cost-effective SoC designs in a timely manner. If you are considering integrating non-volatile memory (NVM) in your next advanced node SoC design, attend this webinar to learn:
Listed below is the industry leader scheduled to speak.
Senior Director, Product Management for NVM IP 草榴社区, 草榴社区
Krishna Balachandran is the senior director of product management for the NVM IP product line at 草榴社区. He is responsible for product and business strategy, marketing operations, product management, promotion, and business development. He has extensive experience in the EDA and semiconductor IP markets and has previously held roles in Product Marketing and Business Development for EDA tools and Semiconductor IP at 草榴社区, Cadence, and Virage Logic. He holds a Master's degree in Computer Engineering from the University of Louisiana, Lafayette and has completed an Executive MBA Certification program from Stanford University.