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For several generations of semiconductor technology, chip designers have derived great benefit from FinFETs, the three-dimensional field-effect transistors (FETs) marked by their thin vertical fins. However, the industry is now running into the limits of how much we can further shrink FinFETs, whilst extracting the speed and power benefits, which are needed for compute-intensive applications like artificial intelligence (AI) and machine learning (ML). Enter the gate-all-around (GAA) transistor architecture, which extends device scaling while increasing chip performance and reducing power.  

GAA devices began to emerge at 3nm and are dominant at 2nm. Currently, high-performance mobile is leading the way in GAA adoption, with hyperscale servers and high-performance CPUs following closely behind. SemiEngineering calls the GAA transistor  As the industry marches into the angstrom era and scaling alone becomes increasingly challenging, GAA transistors—alongside new power distribution schemes and multi-die based design—are poised to help accelerate semiconductor innovation.  

Read on for more details about how transistors have evolved over the years, why GAA devices are the transistor architecture of choice in the angstrom era, and how co-optimizing foundation IP and design flows can help SoC design teams achieve GAA success. 

From Their Planar Roots, Transistors Have Constantly Evolved to Meet New Demands

To achieve the power, performance, and area (PPA) advantages dictated by Moore’s law, transistors have evolved substantially over the years. The development of more than 60 years ago is considered a major step in the creation of integrated circuits (ICs) as we know them today. Enabling the development of transistors on a flat surface, the planar process opened the doors to mass-produced monolithic silicon ICs. While planar MOSFETs have served the industry well for decades, at 20nm, they began to falter because of several factors including short-channel effects.  

The next stage in the transistor evolution was the FinFET, which became commercialized in the first half of the 2010s and grew into dominance at 16nm and below. In a FinFET design, the gate is wrapped around the channel on three sides between the source and the drain. More surface area between the gate and channel means better electrostatic control and reduced leakage compared to planar FETs. For increased drive strength and performance, several fins can be arranged side-by-side on a single FinFET transistor.  

At 3nm and below, variability in the electrical characteristics of FinFET devices starts to explode, creating the need for the new GAA technology. In GAA devices, the gate wraps around all four sides of the transistor for even better electrostatic control of the device. The devices are constructed as a series of (thin, alternating layers of silicon and silicon germanium) which form the transistor channel; gate material surrounds the nanosheet channel on all sides, allowing better control of the current flow through the channel and improved leakage. These structures are stacked, resulting in a vertical form factor that accommodates more active transistors in the same footprint. Another advantage of GAA devices over FinFET is that the drive current is not restricted to coarse multiples governed by the number of fins (1,2 or 3). Instead, the current can be “tuned” to an optimum value by varying the width of the GAA device, which helps SoCs using this technology to save power. GAA transistors can also be constructed with nanowires, where the nanowires are horizontally suspended on landing pads formed on the substrate. These nanowires, surrounded on all sides by the gate, act as the channel for the flow of current. In the future, GAA devices may be replaced by complimentary FET (CFET) devices, where the NMOS and PMOS GAA FETs are placed vertically on top of one another, further increasing the overall transistor density.

Figure 1: Gate-all-around transistors bring benefits including enhanced electrostatic control. (Source: 草榴社区)

Planar, FinFET, and GAA transistors are each likely to continue playing essential roles in chip design, since not every SoC function makes sense to implement in the most advanced nodes. In fact, the increasing popularity of multi-die designs can bring together a heterogeneous set of dies, or chiplets, consisting of any of these transistor types to meet the performance, power, and cost envelopes of the target functions within the overall SoC solution. 

Power Distribution Considerations in the Angstrom Era

The increase in power density that’s achievable at the bleeding edge using GAA transistors requires a substantial amount of power redistribution across the die to prevent IR-drop issues at a given active transistor. The introduction of backside power distribution addresses this problem in a revolutionary way by transferring the power distribution task to the underside of the wafer (a.k.a., the backside of the die). Instead of having many layers of thick metal on wiring on the top surface of the die, above the transistors, this problem can be simplified and shifted to the rear of the die.

Figure 3: This diagram depicts a conventional top-side power distribution network. (Source: 草榴社区)

Backside power distribution greatly reduces resistance to the transistor source, since the connection to that source can be made directly through the back of the wafer rather than through a deep cascade of vias from the thick top metal layers on the topside of the die. In other words, the transistor can access its current more easily through this less resistive topology. This approach eliminates the need for extensive power resource allocation on the top side of the die; therefore, the metal scheme can be simplified and the resources reallocated and optimized for signal routing. These changes can simultaneously improve an SoC’s ability to distribute power, reduce IR-drop, and significantly help improve routability. The value these benefits bring to SoC designers cannot be understated.  

Figure 4: Example back-side power distribution network. (Source: 草榴社区)

What Needs to Be Done to Prepare Chip Designers for GAA Transistors?

From the potential for greater variability to parasitic extraction and modeling accuracy requirements, there’s an array of . This is where high-quality IP and electronic design automation (EDA) flows are essential. In particular, co-optimization between the IP and the SoC design and verification tools can help design teams extract the optimum out of the most advanced processes, putting them on a path to achieve their ever more demanding PPA targets.  

With our 20-year history of developing Foundation IP  from the planar to FinFET eras, while working with hundreds of customers to understand their implementation requirements and design tradeoffs, 草榴社区 has the deep expertise customers need to make the most of new transistor technologies as we enter the GAA era. 草榴社区 2nm GAA Foundation IP is already being sampled by customers, and we are working with multiple foundries to align our IP to their GAA processes. Our IP is co-optimized with 草榴社区 EDA flows, and we can provide a uniquely tunable solution to our customers.  

On the EDA side, 草榴社区 Fusion Design Platform?, an integrated and golden-signoff-enabled RTL-to-GDSII design flow, has been qualified for GAA process technologies at major foundries. In addition, 草榴社区 has collaborated with foundries to optimize our AMS Design Reference Flow, based on 草榴社区 Custom Design Platform, for the GAA process.  

As Moore’s law faces tougher and tougher challenges, engineers continue to devise ways to extract the PPA benefits needed for demanding applications like AI and high-performance computing. GAA transistors represent one of the latest innovations that, alongside new power distribution schemes and chiplet-based design, are enabling technology to continue SoC scaling and propel the era of pervasive intelligence.