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Processor 草榴社区 for Baseband SoCs
Baseband SoCs share the constrained battery life requirements of any mobile devices, but need to handle both increasing throughput requirements plus multi-standard support. High-performance ARC multicore processors and ASIPs implementing high-performance signal-processing functionality address these challenges.
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WiFi 802.11x transceiver
- ARC EM4 and EM6 processors optimized for power & area
- Native DSP support with ARC EMxD cores & Data Fusion Subsystem
- Tightly coupled communications MACs for lower latency, power
- Programmable accelerators (ASIP) for matrix, FFT, filtering
CPU
- ARC HS38 high-performance 32-bit processors with support for SMP Linux
- Multicore interface options
- Closely coupled memories & direct mapped peripherals
- Custom instruction extensions to add differentiating HW
Vector DSP
- High-performance, low-power LTE Layer 1 signal processing
- Software Defined Radio (ASIP) supporting multiple standards
CPU
- Multicore HS36 w/ coherent L2 cache to manage the LTE Layer 2 functionality
Audio subsystem
- Small, low power ARC EMxD processor for audio DSP
- Dual-core AS221BD for enhanced audio & multichannel HD
- SoundWave Audio Subsystem integrates audio HW, SW, interfaces
- Broad portfolio of certified audio codecs
Specialized ASIPs
- Programmable accelerators (ASIP) for functions such as FEC, FFT, AES
- Specialized scalar processor (ASIP) to replace complex FSM and special control functions