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Arm recently announced the availability of the next iteration of the Arm? AMBA? 5 AXI and APB – (AXI-J) and (APB-E). These new specifications introduce several exciting features related to the latest Arm architecture and optimized transaction flows.
草榴社区, a close partner of Arm, offers a broad set AMBA protocol solutions for early modelling, design, implementation, verification, validation, and system bring-up. 草榴社区 leading verification solutions for Arm protocols cover a full range of AMBA5 specifications including next generation AMBA5 CHI-F, ACE5, ACE5-Lite, AXI5, AXI5-Lite, AHB5, APB5, and AXI5 Stream. 草榴社区’ verification automation solutions also offer testbench generation with 草榴社区 VC AutoTestbench and performance verification of Arm based SoCs with 草榴社区 VC AutoPerformance.
“草榴社区 offers comprehensive protocol verification solutions for all existing and next-generation AMBA specifications, including AMBA 5 AXI-J and APB-E,” said Vikas Gautam, vice president of R&D for the 草榴社区 Systems Design Group. “Our verification solutions leverage 草榴社区 leading IPs to drive best-in-class verification credibility, and our offerings for simulation, emulation and prototyping platforms ensure that our customers get end-to-end IP to SoC level verification closure. By working closely with Arm to deliver and deploy first-in-industry customer-proven solutions, we enable the market makers to adopt the latest specifications rapidly.”
This blog will explain the key features of the recent AMBA AXI-J and APB-E release.
The Arm AMBA AXI-J specification brings a range of new Arm architecture features and additional enhancements. It is developed on the foundation of the existing AMBA AXI Issue H (AXI-H.c) specification, which we explored in our previous blogs on the AXI5 and ACE5-Lite protocols. These protocols are capable of operating in conjunction with the AMBA5 CHI-F protocol within a design. Please refer to our blog on the AMBA5 CHI-F VIP for more details.
As on-premises workloads move to the cloud and utilize personal data, the need for privacy-enhancing computation methods in untrusted or shared environments is growing. Armv9 Confidential Compute Architecture (CCA) addresses this with hardware-based secure computation, including Realm Management Extensions (RME) for trusted, dynamic, and attestable execution regions. The following are the salient features of RME.
Write Deferrable Transactions: This transaction is introduced to support the handling of PCIe Gen5 Deferrable Memory Write (DMWr) transactions. It is a 64-byte atomic write request that can be rejected by the completer. The completer has the option to reject the request and issue a Defer response to the requester. The requester can then repeat the write request.
Page-Based Hardware Attributes (PBHA): PBHA values from page tables control various hardware system components during address translations. All translations to a specific physical address should provide the same 4-bit PBHA value to guarantee predictable results.
Other introduced features include: Subordinate Busy, Subsystem Identifier, Unstash Transaction, Invalidate Hint Transaction, Caching Shareable Lines, and Untranslated Transactions V3.
The Arm AMBA APB-E specification is an extension of the AMBA APB5 Issue D (APB-D) specification. APB-D is the first version supporting the APB5 protocol features such as user signalling, wake-up signalling and Interface Parity for functional safety (FuSa). Several leading automotive semiconductor suppliers adopt 草榴社区 AMBA VIP solutions including AMBA APB5 VIP to verify the FuSa features in their designs.
APB-E introduces the new Armv9 architecture feature, Realm Management Extensions (RME). The RME feature is already supported by other 草榴社区 industry first AMBA Verification IPs for the protocols AXI5, ACE5-Lite, ACE5-Lite+DVM and CHI-F, which are widely adopted. As discussed earlier in this blog, RME enables the creation of new physical address spaces, namely Root and Realm in addition to existing secure and non-secure physical address spaces. In APB-E, a new signal called PNSE is introduced to work in tandem with the existing signal PPROT[1] to distinguish between these different physical address spaces.
草榴社区 end-to-end protocol verification solutions for AMBA? 5 AXI5, AXI5-Lite, ACE5, ACE5-Lite, ACE5-Lite/DVM, APB5 provide performance analysis and comprehensive system-level debug capabilities to check for functional correctness, data integrity, and cache coherency. In-built sequence collection, functional coverage model, verification plans, and usage examples are included to ensure fast bring-up and achieve wholistic verification closure. 草榴社区 is collaborating with early customers and partners to extend the standard architecture for their next-generation designs with new features available now with latest specifications.
草榴社区 VIP is natively integrated with the 草榴社区 Verdi? Protocol Analyzer debug solution as well as 草榴社区 Verdi? Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. 草榴社区 transactors, memory models, hybrid and virtual solutions based on 草榴社区 IP enable various verification and validation use-cases on the industry’s fastest verification hardware, 草榴社区 ZeBu? emulation and 草榴社区 HAPS? prototyping systems.
More information on 草榴社区 AMBA? VIP and Test Suites is available at