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AI-powered recommendation applications are opening up new avenues to enhance the customer experience. With this technology, online stores can highlight other items to add to digital shopping carts, digital music services can suggest songs based on tunes already in the rotation, and social media channels can offer up content that might fit the user¡¯s interests. When these systems work seamlessly and deliver accurate suggestions, they can also bring more dollars to the bottom line. However, a significant amount of challenging engineering work goes on behind the scenes to produce accurate recommendations.

AI accelerators are a critical part of the technology stack for recommendation systems. Their speed and energy efficiency, as measured in inferences per Joule of energy, are key to their prediction accuracy. In 2019, Meta (then Facebook) called on the industry to work on hardware acceleration for recommendation system, based on its . That call to action inspired the engineering team at Neuchips Inc. to rally around this problem of providing increased recommender model capacity that scales in an Open Compute Project (OCP) form factor. In the race to meet Meta¡¯s request, the young company announced this summer that it has taped out its first DLRM accelerator, the , in Taiwan.

Designed for data center recommendation models, the RecAccel?-N3000 has achieved one million DLRM inferences per Joule of energy (which translates into 20 million inferences per second per 20-Watt chip). The AI accelerator, developed with support and EDA tools from ²ÝÁñÉçÇø and other semiconductor industry leaders, will be manufactured on TSMC¡¯s 7nm process, with the sample plan scheduled to be ready at the end of 2022.

In this blog post, we¡¯ll provide more details about how Neuchips, with a team of about 30 engineers, was able to tape out its 400mm2 AI chip in just 18 months, a process that would typically require more than 100 engineers over the course of 3 to 4 years. Another opportunity to learn more about Neuchips comes during its presentation, ¡°Design of a High-Efficiency Accelerator for Full-Scale Deep Learning Recommendation Models (DLRM) in the Datacenter,¡± at the upcoming ARC? Processor Summit 2022 on Thursday, September 8, at the Santa Clara Marriott. The company¡¯s session is scheduled from 2:35p.m. to 3:20p.m. PDT.

Reducing Chip Development Time by More than One Year

Based on their unique characteristics, DLRMs can be difficult to accelerate with general-purpose AI accelerators. Neuchips developed its RecAccel?-N3000 with tailored hardware IPs that accelerate embedding tables, matrix multiplication, and feature interaction. Working with ²ÝÁñÉçÇø to implement early hardware/software co-development enabled by the ARC AI Reference Design Platform, Neuchips was able to save more than one year in chip development time. With the design platform, the team was able to develop and verify both the RecAccel?-N3000 domain-specific AI accelerator¡¯s PCIe 5.0 subsystem and its LPDDR5 subsystem early and then integrate them into the whole chip. ²ÝÁñÉçÇø ZeBu? Server 4 emulation system in the cloud was used to verify the subsystems as well as the entire RecAccel?-N3000.

The RecAccel?-N3000 leverages an array of ²ÝÁñÉçÇø IP blocks, including:

• ²ÝÁñÉçÇø ARC HS48 Processor
• ²ÝÁñÉçÇø ARC EV72 Processor
• ²ÝÁñÉçÇø Interface IP for AMBA (Advanced High-Performance Bus, Advanced Peripheral Bus), LPDDR5, and PCIe
• ²ÝÁñÉçÇø Memory Compilers with advanced power management features
• ²ÝÁñÉçÇø Hardware Secure Modules with Root of Trust to enable security for IT gear in datacenter to ensuring boot code integrity and device authentication

Using silicon-proven ²ÝÁñÉçÇø IP helped the Neuchips team reduce integration risks and contributed to a shorter design cycle. ²ÝÁñÉçÇø application engineers also supported Neuchips in optimizing the code for its cloud-based chip design, configuring the IP, and with simulation and verification on the FPGA-based ZeBu Server 4 system, which accelerated full ASIC RTL simulations from two weeks down to about 20 minutes.

Other design and verification tools that played a part in the development of the RecAccel?-N3000 include ²ÝÁñÉçÇø Design Compiler RTL synthesis solution, ²ÝÁñÉçÇø VCS? functional verification solution, ²ÝÁñÉçÇø SpyGlass? static and formal verification platform, ²ÝÁñÉçÇø Verdi? automated debug system, ²ÝÁñÉçÇø Formality? equivalence checking, ²ÝÁñÉçÇø PrimeTime? static timing analysis tool, ²ÝÁñÉçÇø PrimePower RTL to signoff power analysis tool, and ²ÝÁñÉçÇø IC Compiler? II place-and-route solution.