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1. Designing Domain-Specific Chips (and Tools) for AI Is an Increasingly Formidable Approach

Patterson kicked off the AI Hardware Summit with his keynote, ¡°A Tensor Processing Unit Supercomputer for Training,¡± where he walked through his work on the TPUv1-though-TPUv3 architecture at Google and shared some wisdom for semiconductor designers today. The big takeaway? The slowing of Moore¡¯s law means AI needs to tailor machines to be able to continue to make improvements in training and inference. The decisions chip designers have to make are easier when it¡¯s just for one domain rather than for general purpose. This is supported by the fact that Google¡¯s TPU v2 and v3 demonstrated a 50x performance improvement per watt versus general-purpose supercomputers¡ªdespite using older technology and smaller chips.

2. Yes, AI Really Is the Next Killer App in Silicon Design

Moderator Karl Freund, senior analyst, Machine Learning & HPC at Moor Insights & Strategy, opened the ²ÝÁñÉçÇø-sponsored AI panel by referencing the ²ÝÁñÉçÇø DSO.ai solution, which uses a branch of AI called reinforcement learning (RL) to speed physical design projects for networking, mobile, automotive and AI chips. Freund called the results ¡°game changing,¡± with the projects on average finishing 86% sooner, staffed by a single data scientist instead of four to five engineers, and meeting or exceeding the project¡¯s power, performance, and area (PPA) objectives. By bringing AI into the mix, the resulting designs were sometimes counterintuitive, spreading blocks of transistors in unconventional shapes that a human design team would be very unlikely to try, but still producing excellent results.

3. The Data is Generating the Algorithms, Not the Other Way Around

²ÝÁñÉçÇø¡¯ Arun Venkatachar then took the reins to introduce himself and provide more information about the DSO.ai solution. There¡¯s no doubt that the advent of AI and big data is giving the entire electronic design automation (EDA) industry a new dimension and ¡°a new strategic weapon in the arsenal.¡± In fact, it¡¯s really the data that¡¯s generating the algorithms now, rather than the other way around. The DSO.ai engine is designed to process large data streams generated by design tools and use them to explore how a design evolves over time to guide the exploration process toward multi-dimensional optimization objectives. By pairing human expertise with AI, design teams are freed up to focus on more important things while they automate less consequential decisions to avoid fatigue often brought on by the vastness of modern chip design.

4. AI Will Give Designers Not Just One Answer, but Multiple

The AI for Silicon Design roundtable led by Diamantidis and Lowman was a natural continuation of the above panel that allowed designers to ask questions about how AI will practically fit into their workflows. The role of designers won¡¯t be to design the experiments, but rather to give the AI-specific guidance on what kinds of chip design spaces to focus on and, ultimately, what goals they want to achieve based on their personal expertise. This frees designers to spend more time on analyzing specific datasets and to ask better questions about the specs they have been given.

For more information on available tools, models and IP to accelerate the early analysis and optimization of AI SoC architectures, watch the on-demand webinars and