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If it seems that AI is everywhere all at once these days, it’s not your imagination. From our smart speakers and web searches to arduous pursuits like climate change modeling and vaccine discovery, AI is optimizing and accelerating processes in a wide array of areas. In the chip design world, intelligence is providing an answer to the complicated challenges facing the semiconductor industry, from silicon engineering talent shortages to growing chip design complexities and aggressive time-to-market targets.
There was no shortage of insights into the challenges and opportunities of AI in the semiconductor industry during the recent SNUG Silicon Valley 2023 conference in Santa Clara. At one of the event’s lunchtime panels, “How AI Is Driving the Next Innovation Wave for EDA,” Karl Freund, founder and principal analyst at Cambrian-AI Research, moderated a lively discussion featuring:
- Thomas Andersen, VP of engineering in the 草榴社区 EDA Group
- Monica Farkash, principal member of the technical staff at AMD
- Savita Banerjee, DFT manager at Meta and SNUG Technical Committee chair
- Vikas Agrawal, director of engineering at NVIDIA
Read on to learn how these experts envision the role of AI in addressing key challenges across the chip development cycle.
Pioneering AI in EDA Tools
Thomas Andersen kicked things off by highlighting some of the challenges impacting the semiconductor landscape today: the march to angstrom-level scaling, the need to reduce power consumption by 1000x, multi-die architectures and other growing design complexities—all happening in the face of semiconductor talent shortages. A predicts a need for more than one million additional skilled workers in the industry by 2030, which equates to more than 100,000 annually. However, the consultancy also notes that there are fewer than 100,000 graduate students enrolled in electrical engineering and computer science programs in the U.S. each year.
A productivity boost is in order, Andersen said, and AI provides a natural answer. During the first day of the SNUG Silicon Valley conference, 草榴社区 introduced 草榴社区.ai, the industry’s first AI-driven full-stack EDA design suite, spanning system architecture to verification, implementation, signoff, test, and silicon manufacturing. In 2020, 草榴社区 led the way to AI in electronic design automation (EDA) tools with the launch of 草榴社区 DSO.ai?, the first AI application for chip design. Now, 草榴社区.ai brings new capabilities into the fold:
- Next-generation DSO.ai for 2x faster turnaround time, 20% better quality-of-results, and reduced compute effort with automated machine learning permuton optimization.
- 草榴社区 VSO.ai AI-driven verification solution for faster, better verification coverage and debug.
- 草榴社区 TSO.ai autonomous AI application for semiconductor test for faster and more optimized test program generation.
- And much more in the pipeline, with development underway to bring AI into areas such as analog design, mask synthesis, architecture optimization, engineering change order closure, RTL design, and process space optimization.
Challenges—and Opportunities—with AI in Chip Design
Noting the massive impact that AI is already happening in EDA and beyond (such as with the booming popularity of the ChatGPT generative AI-based chatbot), Freund wanted to hear the panelists’ thoughts on the challenges and opportunities ahead.
“It’s more about how we can use the knowledge we’ve gained from process manufacturing data to influence some of the design decisions we make that would then optimize the overall design space,” said Banerjee, representing the test side of the business.
Farkash highlighted knowledge as a key challenge, as well as an opportunity. Afterall, applying AI to different chip design solutions requires a deep understanding of how it all works. At the same time, it also presents a chance to explore where AI and machine learning can be applied. “Wherever you look, it’s just opportunity,” she said. “It’s everywhere.”
Agrawal noted that, had he been asked the same question six months ago, he would’ve had a different answer. However, he said, ChatGPT has proven that AI is ahead of what we’ve expected. “What else can AI do?” Agrawal asked. “To me the sky’s the limit. Whatever I say today, it’ll be wrong in two to three years!” The challenge, he said, is to find talented people who are interested and motivated to work in EDA, especially as AI touches so many areas, and to optimize the compute platform for EDA algorithms.
Another challenge for the EDA industry in particular is, it doesn’t have an unlimited amount of data for AI training, Andersen noted. To overcome this, 草榴社区 has focused on applying reinforcement learning to actual designs on the fly, eliminating the need to pretrain on data. Another obstacle are the naysayers who are skeptical at how AI could arrive at better results than they can, but those who adopt AI are the ones who will ultimately be successful, Andersen said. In fact, AI also presents a solution to knowledge gaps that occur when people leave an organization, he added.
Does ChatGPT Help or Hurt the Cause?
While tools like ChatGPT are having their moment, there also is a fair amount of debate over the impact of this technology. Freund asked the panelists to weigh in on whether generative AI could be a source of future productivity gains in chip design.
Even with significant issues like accuracy to iron out, Farkash noted that AI is huge for productivity and for allowing engineers to focus on solving more complicated problems. There will always be something else that needs to be done, so we can only be happy that AI will help us reach a different level of achievement, she indicated.
Agrawal pointed out that while tools are now available to compile C code into machine code, engineers are still writing the C code. Chip engineers are still around and will continue to be. Yet, there are ways now to truly aim higher. “Can I say, ‘Hey, NVIDIA: build me a chip?’ I think that’s the moonshot,” said Agrawal. “ChatGPT changes everything in what we’ve thought about AI and its limitations.”
Andersen is cautiously optimistic about the role of generative AI in chip design, explaining, “In our world, there are multiple challenges. GPT requires a huge amount of training data. And the ‘quality’ of the data is unclear, so training data and quality are two things we need to overcome.” Farkash pointed out that a generative AI tool could generate what’s needed for different phases of chip design and verification, but people are needed who can optimize it.
Looking at the big picture, Andersen sees optimizing the entire stack of chip design as the right direction. “There’s big potential to use AI and optimize techniques to make decisions that have a broader impact that you may only see later on. It’s like building a house, you have to make the right architectural decisions before you can optimize the details,” he said.
Working Hand-in-Hand with Technology to Create New Technologies
Overall, the panel was upbeat about how AI can enhance productivity and outcomes in chip development. If engineers feel threatened by progress, perhaps they wouldn’t be using some of the tools that are commonplace today. Perhaps they would even expect to do the same job in the same way over decades.
“But then we’re not really engineers,” Banerjee said. The key, she said, is to harness new technologies while finding ways for engineers to add value. In her view, technologies “need checks and balances without discouraging human creativity. How can we co-exist and fuel productivity and creativity of humans and not outsource it all to the bots?”
Human creativity could very well be a big winner in all of this. It’s not uncommon for engineers to sacrifice one benefit to gain another; for example, productivity for additional power, performance, and area (PPA) advantages. What if they no longer have to make this tradeoff? Imagine the possibilities.