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Under the hood of our rapidly evolving lifestyle of smart cars, smart homes, smart phones—Smart Everything—are semiconductors. And because our applications are getting more advanced and intelligent all the time, the chip is getting more complex and intelligent, too. To meet the chip design opportunities and challenges of the moment, semiconductor innovation goes far beyond packing more logic into silicon—it requires creative design approaches that will fast-forward our ability to seize the opportunities and resolve the challenges we face. To get to the future faster means using AI for the chip design process, a hot topic at earlier this spring.
Mainstage keynotes set the tone of the event with 草榴社区 Chairman and CEO Aart de Geus kicking things off with his talk, Catalyzing the Impossible, including special guest, Chairman and CEO Satya Nadella. , the director of the , zeroed in on the topic of AI in her talk, AI and Its Impact on Humanity. Other AI track highlights included an engaging fireside chat, AI’s Next Act – Impact on Chip Design Today and Vision for Future, between Tony Han, engineering director at and Stelios Diamantidis, senior director of AI solutions and strategy at 草榴社区, as well as multiple customer case studies using 草榴社区 DSO.aiTM, the industry’s first AI application for chip design. The AI track experts from 草榴社区, MediaTek, as well as , , , and , illustrated the compelling value and opportunities that AI has to offer the semiconductor industry.
Here are some AI takeaways from SNUG Silicon Valley 2022:
1. Along with the Challenges, AI Technology Presents Great Opportunities for Humanity
In her talk, AI and Its Impact on Humanity, Dr. Rus painted a picture of what an AI-enabled world could look like in your day-to-day life. The takeaway was that AI can improve lives whether robots are helping plant your garden or the technology is generating a bespoke outfit for you on demand. AI also can impact the world in much bigger ways, helping humanity with everything from medicine to climate change. But our excitement should be tempered with some caution: humanity can realize the advantages of AI only if we proceed with wisdom and responsibility to surmount its inherent challenges. Dr. Rus summed it up by saying, “It is our privilege to be the only species so advanced, so aware, so capable of building these extraordinary tools. But that also means it’s our responsibility to put them to good use. I remain convinced that we have the power to harness the power of AI, machine learning, and robotics tools to ensure a better future for all humanity and for everyone else on our planet.”
“It is our privilege to be the only species so advanced, so aware, so capable of building these extraordinary tools. But that also means it’s our responsibility to put them to good use. I remain convinced that we have the power to harness the power of AI, machine learning, and robotics tools to ensure a better future for all humanity and for everyone else on our planet.”
– Dr. Daniela Rus, Director of CSAIL, MIT
2. Leveraging AI at Scale Accelerates Chip Design Innovation, Leads to 1000x Better Compute
The semiconductor industry’s first attempt to use AI in the design process started with the award-winning DSO.ai solution. Launched in 2020, DSO.ai has already been leveraged for dozens of customer tapeouts and is currently deployed at 6 of the top 10 semiconductor companies worldwide. Using a multi-objective reinforcement learning engine, DSO.ai technology autonomously searches design spaces for better power-performance-area (PPA) solutions, massively scaling the exploration of choices in chip design workflows, while automating many menial tasks. By delivering results previously deemed infeasible within weeks, and with a single engineer versus several experts, DSO.ai technology enables engineering teams to achieve ‘AI-grade’ productivity. This allows them to deploy resources to more value-added work, such as product differentiation.
In order to tackle systemic complexity inherent in achieving 1000x better compute, AI systems must have the ability to apply learnings autonomously across designs to achieve scale. In the session, AI’s Next Act – Impact on Chip Design Today and Vision for Future, attendees learned about several real-world design results achieved using DSO.ai, the industry’s only cross-design learning system. In all cases, the DSO.ai solution was able to achieve better PPA with lower effort, even with no prior learning (cold-start). And it quickly became more efficient as it trained. When learnings were applied for variants of the same design (warm-start) and later for new, derivative designs (cross-design), DSO.ai technology delivered results much faster and with significantly less compute, eventually achieving auto-convergence.
So, what is next for AI in chip design? According to Tony Han from MediaTek, implementing turn-key ASIC tapeouts and supporting more than 4000 global users, the opportunities extend all the way from silicon manufacturing to systems—essentially AI everywhere. In Tony’s words, “…we are moving from developing product for machine learning to applying machine learning for product, technology, and company operations.”
“…we are moving from developing product for machine learning to applying machine learning for product, technology, and company operations.”
– Tony Han, Engineering Director, MediaTek
3. Beyond Optimizing Flow PPA – You Can Do So Much More with AI for Chip Design
When you first begin working with the DSO.ai solution, you might typically focus on optimizing design flow for timing, congestion, or power optimizations. But as you work with the tool, you’ll discover that you can do so much more:
- Floorplan exploration to shrink the die and save on area
- Power network optimization to reduce IR-drop
- Optimal library cell selection to improve runtime and performance
- Clock tree implementation
- Voltage scaling and design technology co-optimization (DTCO)
The possibilities for autonomous chip design are truly endless! Sessions during the conference drove all this home with real-world case studies. Sony Designs presented Maximize PPA Benefits Using DSO.ai, demonstrating significant area reduction across several of their CMOS sensor designs at 40nm, including the first production use for cross-design learning. In Leveraging Synopsys DSO.ai to Achieve Optimized PPA and TAT, Intel showed users how they chose the optimal standard-cell libraries for a faster RTL-to-GDS design closure in FPGA-based designs for the latest process nodes. And, in AI-Driven Voltage and Frequency Optimization: Maximizing Performance and Power for Mobile CPUs, attendees learned from Samsung how they optimized the best voltage and fMAX for the latest 4nm, Arm big CPU core in order to achieve maximum performance per watt.
Of course, the 草榴社区 IP team also shared their experience with DSO.ai technology, which they used to build a custom application to optimize an RDL bump map to reduce IR-drop. They achieved this in a day versus weeks.
Bridge to a New Level of Innovation
For those just getting started using the DSO.ai solution, there is design start help, including a library of AI-driven physical design applications which provide customizable design spaces, target metrics, and scripts to enable you to quickly explore the power of the technology .
AI is helping designers bridge to a new level of innovation in chip design across all process nodes and market segments, opening our future to a world of possibilities as a result. We hope to see you at next year’s SNUG Silicon Valley. In the meantime, registered 草榴社区 users can access the SNUG Silicon Valley 2022 conference sessions on demand.