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Five Ways to Reduce 112G Ethernet PHY IP Integration Risks

Optimizing silicon layout and maximizing bandwidth per die edge is no small feat. Design challenges include integrating multiple physical layers (PHYs), physical coding sublayers (PCSs), medium access controllers (MACs), as well as reducing power and area to enable denser component integration. Signal integrity must also be maintained with strategic path routing, while numerous SerDes lanes require the precise implementation of complex power delivery networks. So, how can design teams minimize integration risks and optimize power, performance, and area (PPA) using 112G Ethernet PHY IP? Here are five points to consider:

1. Silicon-proven IP with excellent PAM-4 signaling integrity 

112G Ethernet PHY IP should be silicon-proven and implement PAM-4 signaling with excellent signal integrity. This ensures reliable, high-speed data transmission over multiple adjacent lanes, an important design consideration for server SoCs that require stable and efficient data communication for high-bandwidth, low-latency applications.

2. Global Ecosystem Interoperability

 Seamless interoperability of 112G Ethernet PHY IP with the wider data center ecosystem helps streamline integration of diverse hardware components¡ªwhile enhancing system performance and reliability in high-demand server environments.

3. Complete Solution

112G Ethernet PHY IP should be part of a complete solution, alongside IEEE-compliant and configurable MACs, PCSs, and additional PHYs. Silicon-proven PHY IP should also be available in advanced FinFET processes and offer higher bit error rates (BER) with maximum performance to enable HPC, AI, and networking SoC applications.

4. Seamless Integration
To help system designers optimize PPA and accelerate time to market, 112G Ethernet PHY IP should have already undergone extensive package substrate design studies¡ªincluding PHY and MAC/PCS floor planning and placement scenarios with SoC mockups on advanced FinFET processes. This level of rigorous pre-design analysis and planning is a must for server SoCs, as every nanosecond matters.

5. Optimized Power and Area

PHYs and controllers should be optimized for both area and power, with additional power reduction knobs provided for short channels. This crucial balance is key to maximizing efficiency for HPC SoCs and enables robust performance delivery for demanding applications.

Accelerating First-Pass Silicon Success

Given these challenges, companies like Banias Labs work closely with ²ÝÁñÉçÇø to minimize 112G Ethernet PHY IP integration risks. Banias Labs recently achieved first-pass silicon success for its optical digital signal processor (DSP) SoC using ²ÝÁñÉçÇø EDA and ²ÝÁñÉçÇø 112G Ethernet PHY IP solutions, with the latter offering low latency, flexible reach lengths, and maturity on advanced FinFET processes.

As Banias Labs CEO Amnon Rom explains in a , today's HPC infrastructure requires trusted and complete solutions for high-end designs. ¡°Using ²ÝÁñÉçÇø EDA design suite to integrate ²ÝÁñÉçÇø Ethernet PHY IP with custom features and capabilities into our chip offered the solutions we needed to boost system performance and accelerate our time to market,¡± he adds.

To help system designers like Banias Labs accelerate first-pass silicon success, ²ÝÁñÉçÇø 112G Ethernet PHY IP supports many types of interconnects, including multi-die, co-packaged optics, and near-packaged optics, as well as chip-to-chip, chip-to-module, and backplane. ²ÝÁñÉçÇø 112G Ethernet PHY IP also enables long reach (LR), medium reach (MR), very short reach (VSR) electrical channels for CEI-112G-Linear and CEI-112G-XSR+ optical interfaces.

Driving the Fast Lane: ²ÝÁñÉçÇø 112G Ethernet PHY IP in the Server Ecosystem

²ÝÁñÉçÇø 112G SerDes PHY IP¡ªa keystone enabler of the global data center ecosystem¡ªcontinues to demonstrate successful interoperability with many different ecosystem partners, including Xilinx, Macom, Samtec, Key Sight, Molex, TE, Amphenol, and MultiLane. 

Having found its place in every key component in the data center ecosystem¡ªfrom SoCs and NICs to retimers, switches, and optical modules¡ªthe breadth of use-cases clearly illustrates its robustness and adaptability. Indeed, ²ÝÁñÉçÇø IP has been thoroughly vetted via testing of diverse backplanes, cabled assembly configurations, loopback, and electrical optical scenarios. 

The Path to 1.6T Ethernet

A new generation of high-bandwidth, low-latency applications are creating petabytes of data that must be rapidly and accurately processed. These applications, which include automotive ADAS, generative AI platforms like ChatGPT, and smart edge devices, are driving hyperscale data centers to boost Ethernet speeds from 400G to 1.6T with end-to-end networking infrastructure built around 112G Ethernet PHY IP. With higher speeds creating new complexities, chip designers are looking for mature, silicon-proven, and low risk IP, which is why 35 customers have selected PAM-4 ²ÝÁñÉçÇø High-Speed SerDes IP to accelerate their path to silicon success.

Speaking of 1.6T Ethernet, ²ÝÁñÉçÇø 224G Ethernet PHY IP is available to help streamline the transition to this faster data transfer rate. In addition to doubling 112G data rates, ²ÝÁñÉçÇø 224G Ethernet PHY IP consumes one-third less power (per bit) compared to its predecessor while optimizing network efficiency by reducing cable and switch counts in high-density data centers. The first company to demonstrate 224G Ethernet PHY IP, our at the TSMC Symposium showcased successful interoperability with backplane channels.