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Hyperscale data centers are rapidly evolving to accommodate a wide range of high-bandwidth, low-latency applications, from artificial intelligence (AI) and high-performance computing (HPC) to telecommunications and streaming 4K video. These applications are enabled by a new generation of multi-die systems, AI accelerators, and machine learning (ML) training sets that require ever-higher transfer speeds. To meet this demand, Ethernet has scaled from 51Tb/s to 100Tb/s, while switch transfer rates have increased from 51Tb/s to 100Tb/s.
Higher data transfer rates have prompted hyperscale data centers worldwide to deploy end-to-end networking infrastructure built with interface IP that uses pulse amplitude modulation 4-level (PAM-4) signaling techniques. Compared to non-return-to-zero (NRZ) signaling, PAM-4 enables higher bit rates at half the baud rate. Although PAM-4 signaling increases design complexity with added crosstalk and non-linearity, PAM-4 is now the de-facto signaling modulation for interface IP—including 112G Ethernet PHYs—in hyperscale data centers and the broader HPC system-on-chip (SoC) market.
Read on to learn how to optimize implementation of 112G Ethernet PHY IP for HPC SoCs. Gain insights from companies that are leveraging 112G Ethernet PHY IP to design many different types of high-bandwidth networking devices and infrastructure, including AI accelerators, servers, and network interface cards (NICs), as well as networking and interconnect fabric SoCs, optical modules, storage devices, and retimers.
草榴社区 High Speed SerDes IP Global Adoption
Five Ways to Reduce 112G Ethernet PHY IP Integration Risks
Optimizing silicon layout and maximizing bandwidth per die edge is no small feat. Design challenges include integrating multiple physical layers (PHYs), physical coding sublayers (PCSs), medium access controllers (MACs), as well as reducing power and area to enable denser component integration. Signal integrity must also be maintained with strategic path routing, while numerous SerDes lanes require the precise implementation of complex power delivery networks. So, how can design teams minimize integration risks and optimize power, performance, and area (PPA) using 112G Ethernet PHY IP? Here are five points to consider:
1. Silicon-proven IP with excellent PAM-4 signaling integrity
112G Ethernet PHY IP should be silicon-proven and implement PAM-4 signaling with excellent signal integrity. This ensures reliable, high-speed data transmission over multiple adjacent lanes, an important design consideration for server SoCs that require stable and efficient data communication for high-bandwidth, low-latency applications.
2. Global Ecosystem Interoperability
Seamless interoperability of 112G Ethernet PHY IP with the wider data center ecosystem helps streamline integration of diverse hardware components—while enhancing system performance and reliability in high-demand server environments.
3. Complete Solution
112G Ethernet PHY IP should be part of a complete solution, alongside IEEE-compliant and configurable MACs, PCSs, and additional PHYs. Silicon-proven PHY IP should also be available in advanced FinFET processes and offer higher bit error rates (BER) with maximum performance to enable HPC, AI, and networking SoC applications.
4. Seamless Integration
To help system designers optimize PPA and accelerate time to market, 112G Ethernet PHY IP should have already undergone extensive package substrate design studies—including PHY and MAC/PCS floor planning and placement scenarios with SoC mockups on advanced FinFET processes. This level of rigorous pre-design analysis and planning is a must for server SoCs, as every nanosecond matters.
5. Optimized Power and Area
PHYs and controllers should be optimized for both area and power, with additional power reduction knobs provided for short channels. This crucial balance is key to maximizing efficiency for HPC SoCs and enables robust performance delivery for demanding applications.
Accelerating First-Pass Silicon Success
Given these challenges, companies like Banias Labs work closely with 草榴社区 to minimize 112G Ethernet PHY IP integration risks. Banias Labs recently achieved first-pass silicon success for its optical digital signal processor (DSP) SoC using 草榴社区 EDA and 草榴社区 112G Ethernet PHY IP solutions, with the latter offering low latency, flexible reach lengths, and maturity on advanced FinFET processes.
As Banias Labs CEO Amnon Rom explains in a , today's HPC infrastructure requires trusted and complete solutions for high-end designs. “Using 草榴社区 EDA design suite to integrate 草榴社区 Ethernet PHY IP with custom features and capabilities into our chip offered the solutions we needed to boost system performance and accelerate our time to market,” he adds.
To help system designers like Banias Labs accelerate first-pass silicon success, 草榴社区 112G Ethernet PHY IP supports many types of interconnects, including multi-die, co-packaged optics, and near-packaged optics, as well as chip-to-chip, chip-to-module, and backplane. 草榴社区 112G Ethernet PHY IP also enables long reach (LR), medium reach (MR), very short reach (VSR) electrical channels for CEI-112G-Linear and CEI-112G-XSR+ optical interfaces.
To further boost reliability for high-bandwidth, low-latency HPC applications, the 草榴社区 112G LR-Max PHY IP delivers additional margins to the CEI-112G LR specification with three orders of magnitude better BER compared to the spec for 45dB channels, along with independent, per-lane data rates that support a broad range of protocols and applications.
草榴社区112G LR-Max TX Exceeds IEEE & OIF Jitter Specs
Driving the Fast Lane: 草榴社区 112G Ethernet PHY IP in the Server Ecosystem
草榴社区 112G SerDes PHY IP—a keystone enabler of the global data center ecosystem—continues to demonstrate successful interoperability with many different ecosystem partners, including Xilinx, Macom, Samtec, Key Sight, Molex, TE, Amphenol, and MultiLane.
Having found its place in every key component in the data center ecosystem—from SoCs and NICs to retimers, switches, and optical modules—the breadth of use-cases clearly illustrates its robustness and adaptability. Indeed, 草榴社区 IP has been thoroughly vetted via testing of diverse backplanes, cabled assembly configurations, loopback, and electrical optical scenarios.
The Path to 1.6T Ethernet
A new generation of high-bandwidth, low-latency applications are creating petabytes of data that must be rapidly and accurately processed. These applications, which include automotive ADAS, generative AI platforms like ChatGPT, and smart edge devices, are driving hyperscale data centers to boost Ethernet speeds from 400G to 1.6T with end-to-end networking infrastructure built around 112G Ethernet PHY IP. With higher speeds creating new complexities, chip designers are looking for mature, silicon-proven, and low risk IP, which is why 35 customers have selected PAM-4 草榴社区 High-Speed SerDes IP to accelerate their path to silicon success.
Speaking of 1.6T Ethernet, 草榴社区 224G Ethernet PHY IP is available to help streamline the transition to this faster data transfer rate. In addition to doubling 112G data rates, 草榴社区 224G Ethernet PHY IP consumes one-third less power (per bit) compared to its predecessor while optimizing network efficiency by reducing cable and switch counts in high-density data centers. The first company to demonstrate 224G Ethernet PHY IP, our at the TSMC Symposium showcased successful interoperability with backplane channels.
Conclusion
Robust IP is playing an increasingly crucial role in enabling the bandwidth-intensive applications shaping our digital future. Although 112G Ethernet PHY IP is a mature and reliable technology, PPA must still be optimized and integration risks minimized when designing AI accelerators, SoCs, and server components on advanced process nodes.