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What is New with PCI Express 7.0 (PCIe 7.0)?

PCI-SIG announced PCIe 7.0 technology in 2022, with plans to release the full specification by 2025. This development aims to meet the substantial bandwidth demands of data-intensive applications and markets, including AI/ML, networking at 1.6T/800G Ethernet, HPC, and quantum Computing in HPC data centers. PCIe 7.0 will provide a low-latency, low-power, and reliable link between accelerators, processors, NICs, and other components, ensuring efficient connectivity for high-performance computing environments.

• Increased Bandwidth: PCIe 7.0 doubles the bandwidth of PCIe 6.0, reaching speeds of up to 512 GB/s bi-directionally with 16 lanes of 128 GT/s.  This enhanced bandwidth is crucial for handling large volumes of data quickly and efficiently, which is critical for AI and HPC applications.
• Low Latency: With improved signaling rates, PCIe 7.0 reduces latency vital for real-time processing and responsiveness in AI algorithms and high-speed data processing in HPC.
• Compatibility and Scalability: PCIe 7.0 maintains backward compatibility with previous PCIe generations, ensuring interoperability with existing hardware while offering scalability for future upgrades. This is crucial for seamlessly integrating new technologies into existing AI and HPC infrastructures.
• Energy Efficiency: Despite the increased performance, PCIe 7.0 aims to maintain or improve energy efficiency, critical for reducing overall operational costs and the environmental impact in data centers and large-scale computing facilities.
• Advanced Features: PCIe 7.0 introduces new features and optimizations that further enhance its utility in demanding applications, including improved lane margining capabilities, enhanced error detection and reporting mechanisms, and support for emerging technologies such as CXL.
• Channel Reach and Signal Integrity Considerations: The target channel reach for PCIe 7.0 remains the same as PCIe 6.0, with 4¡±-14¡± system routing and 2¡±-4¡± AIC routing in single connection topology, and pad-to-pad channel loss of up to -36dB. To minimize insertion loss and reflection in the Root Complex reference package, improvements in connector insertion loss, return loss, PCB loss, via insertion & return loss, are performed by minimizing crosstalk.

Why is PCI Express Compliance Important?

With the rise of technological advancements, there's a growing demand for faster CPUs, quicker memory solutions, and advanced consumer devices. This amplifies the need for enhanced system interconnectivity and broadened bandwidth. Standards like PCIe serve this very purpose, catering to diverse sectors from data centers and AI/machine learning to cloud solutions.

Within chip design, compatibility across products in the market remains a top priority. PCI-SIG Compliance Testing plays a pivotal role in ensuring this. Manufacturers submit their products to PCI-SIG Compliance Workshops to verify their adherence to crucial PCIe specifications and, crucially, to ensure seamless integration with other ecosystem products, irrespective of the vendor. While companies can undertake in-house tests for cross-vendor compatibility, achieving PCIe compliance offers a more robust validation of a product's interoperability, endorsed by industry frontrunners. Thus, with this compliance seal, developers can proceed with their chip designs, confident in their product's capability to integrate seamlessly with others in the marketplace.