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PCIe, or Peripheral Component Interconnect Express, is a standard for connecting a computer's motherboard with peripherals such as graphics cards, sound cards, and solid-state drives. A PCIe card plugs into a corresponding slot on the motherboard, with types ranging from x1 to x16, indicating the number of data lanes available. More lanes mean higher data transfer rates, akin to more lanes on a highway enabling faster traffic flow. The standard is maintained by the .
For nearly 30 years, PCIe has been crucial for I/O connectivity, offering power-efficient, high-bandwidth, and low-latency communication between computer components. Adopted across various applications—from handheld devices to high-performance computing and data centers—PCIe excels in interoperability, capacity, and bandwidth. Its robust infrastructure also supports other protocols like Compute Express Link (CXL?), leveraging PCIe's software stack and platform connectivity.
PCI Express (PCIe) operates as a serial connection, akin to a network rather than a traditional bus. Instead of a single bus managing data from various sources, PCIe employs a switch directing multiple point-to-point serial connections. Each device has its dedicated connection, eliminating the need for shared bandwidth as with conventional buses. A PCIe lane, crucial for communication between devices or the CPU, consists of two wires: one for incoming data and a second with double the bandwidth for outgoing data. These lanes ensure rapid bit transfer over electrical wires, with the number of lanes in a PCIe device denoted as xN, signifying its bandwidth capacity.
Figure 1: PCI Express Devices
PCIe incorporates high-speed serial communication, point-to-point connections, switch-based architecture, and a packetized protocol. The efficiency of PCIe heavily hinges on link negotiation and training, making the capturing and observation of dynamic link activities fundamental to its debugging. Analogous to the seven-layer OSI model in networking, PCIe operates on a layered architecture (Figure below).
PCIe Architecture includes application, transaction, data link and physical layers.
PCIe Layered Architecture Breakdown
Typical Transactions at Each Layer of PCIe Operation
A PCIe link is established when two devices communicate. As shown in the figure below, both sides have a transmitter (TX) and a receiver (RX). The application layer facilitates data transfer between the root complex/host and the endpoint over this link. The corresponding device driver generates PCIe traffic, which traverses from the transaction layer to the datalink layer, then to the physical layer, and finally to the opposite side of the link.
Anatomy of a PCIe Link
Hyperscale data center service providers must allow faster interfaces, because of this PCIe transitioned from PCIe 5.0 using NRZ to PCIe 6.0 using PAM-4. Using the PAM-4 signaling is critical because Non-Return to Zero (NRZ) signaling is no longer able to support data rates beyond 32G for lossy channels beyond just few decibels (dB) of insertion loss. For further detail, see this article on PAM-4 multi-level signaling and its trade-offs and benefits vs. NRZ.
Compared to NRZ’s two voltage levels, PAM-4 has four voltage levels that result in 12 distinct signal transitions, (six rise & six fall times) creating three district eye openings, as shown in the figure below. Each eye height is 1/3 of an NRZ eye height, causing the PAM-4 signal-to-noise ratio (SNR) to degrade by over 9.5 dB, which impacts the signal quality and introduces additional constraints in high-speed signaling. The 33% smaller vertical eye opening reduces the signal’s tolerance to crosstalk and reflection in PAM-4 resulting in a higher bit error rate.
NRZ vs. PAM4 Signal Transitions and Eye Openings
PCI-SIG announced PCIe 7.0 technology in 2022, with plans to release the full specification by 2025. This development aims to meet the substantial bandwidth demands of data-intensive applications and markets, including AI/ML, networking at 1.6T/800G Ethernet, HPC, and quantum Computing in HPC data centers. PCIe 7.0 will provide a low-latency, low-power, and reliable link between accelerators, processors, NICs, and other components, ensuring efficient connectivity for high-performance computing environments.
With the rise of technological advancements, there's a growing demand for faster CPUs, quicker memory solutions, and advanced consumer devices. This amplifies the need for enhanced system interconnectivity and broadened bandwidth. Standards like PCIe serve this very purpose, catering to diverse sectors from data centers and AI/machine learning to cloud solutions.
Within chip design, compatibility across products in the market remains a top priority. PCI-SIG Compliance Testing plays a pivotal role in ensuring this. Manufacturers submit their products to PCI-SIG Compliance Workshops to verify their adherence to crucial PCIe specifications and, crucially, to ensure seamless integration with other ecosystem products, irrespective of the vendor. While companies can undertake in-house tests for cross-vendor compatibility, achieving PCIe compliance offers a more robust validation of a product's interoperability, endorsed by industry frontrunners. Thus, with this compliance seal, developers can proceed with their chip designs, confident in their product's capability to integrate seamlessly with others in the marketplace.
As the leading provider of interface IP, 草榴社区 continues to enable the whole PCIe ecosystem, from processors and accelerators to flash controller, solid-state drive, retimers, Smart NICs, and switches. 草榴社区 brings over two decades of experience in PCIe IP and more than 3,000 design wins with leading companies. 草榴社区 IP 草榴社区 for PCI Express? (PCIe?) consist of digital controllers, Integrity and Data Encryption (IDE) Security Modules, PHYs and verification IP. The IP solutions are designed to support all required features of the PCIe 7.0 128 GT/s (Gen7), PCIe 6.0 64GT/s (Gen6), PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s, (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1), and latest PIPE specifications.
草榴社区 offers silicon-proven IP solutions for PCIe that provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, AI, and automotive applications. Extensive interoperability testing with third-party products and strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk.
World’s First Complete PCIe 7.0 IP Solution
草榴社区 is at the forefront of this technology revolution with industry's first complete pre-verified PCIe 7.0 IP solution. The standards-based solution, consisting of PHY, controller, IDE security module, and verification IP, provides secure data transfers up to 512 GB/s bidirectional in a x16 configuration to mitigate data bottlenecks. With over two decades of PCI Express experience, 草榴社区 offers designers an early start for next generation HPC and AI SoCs to accelerate the path to production.
High-performance, low-latency connectivity solutions
PCIe 7.0 meets AI's bandwidth needs with 512 GB/s speed and ultra-low latency.
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