草榴社区

Find Bugs Earlier and Reduce Re-spins with Low Power Verification

Power-aware verification of advanced low power designs (analog and digital) is a top concern for products at 32 nm and below. Voltage-aware functional verification in 草榴社区' advanced low power solution is comprised of VCS Native Low Power (NLP) and VC LP, an advanced low power static rules checker that offers comprehensive coverage for all advanced power management functions. 草榴社区' Low Power Verification solution's voltage-aware checking, modeling and simulation technology provides the needed accuracy and verification coverage for all low power designs, including the most advanced mobile SoCs with fine-grained power management. VCS NLP and VC LP supports comprehensive static analysis and checking of UPF power intent, including power state transitions, power shutdown and multi-rail macros and the like, to enable designers to rapidly find and fix low power bugs.