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This bi-annual newsletter provides you with easy access to ASIP related resources. This issue includes the following topics:

• Technology Feature: Architectural Exploration 

• What¡¯s New: 2019.03 Release Update

• Additional Resources: Customer Successes, White Papers

A key challenge for system-on-chip (SoC) designers is to introduce differentiating advantages within the target product's market window.  Designers therefore need to be able to rapidly explore the impact of architectural choices upon their ASIP, by doing three things:

1. Define benchmarks

Benchmarks must be representative of the end application, to enable a quantitative comparison of the architectures being considered. A benchmark must have:

• A functional specification, describing the application kernels that need to be implemented. Benchmarks are usually represented in C for ease of implementation and architectural independence
• An environment describing the stimuli that exercise the benchmark
• Performance metrics such as power, performance, and target frequency

2. Describe a candidate architecture

Request: Designers need a quick and easy way to define a candidate architecture, ideally using a modelling approach that avoids specifying deep implementation details early in the design process.

Solution: In ASIP Designer?, the ASIP is described using nML, a structured architecture description language that efficiently and concisely describes processor architectures at the same level of abstraction as a programmer¡¯s manual. The language is used to define the structural characteristics of the design (registers, functional units, signals, etc.) and the instruction-set architecture. nML also enables users to describe the cycle- and bit-accurate behavior of the datapaths and I/O interfaces.

3. Explore the design space

Design exploration involves evaluating each candidate architecture against the defined benchmarks. There are two main steps to this, described below:

Compiler-in-the-loop?

Request: Designers need to use a compiler to run benchmarks onto each candidate architecture, rather than trying to use time-consuming and error-prone assembly language. It¡¯s also useful to have a cycle-accurate instruction set simulator (ISS) and a profiler to analyze results.

Solution: In ASIP Designer, an ASIP¡¯s nML description is used as an input to the retargetable SDK, which automatically adapts to the defined processor architecture (step 1 in Figure 1). The SDK includes an optimized C/C++ compiler, assembler/disassembler, linker, cycle-accurate as well as instruction-accurate instruction-set simulator with powerful profiling capabilities, and graphical debugger.

It is possible for the compiler to adapt to the details of each candidate¡¯s architecture because its compiler optimizations are implemented in a generic way. Other compiler frameworks, such as GNU¡¯s GCC, need an architecture-specific compiler backend for each candidate. The immediate availability of a compiler is the key enabler for rapid architectural exploration and iteration.

Having a compiler in the loop also means software authors can provide feedback to the ASIP designer, and the processor¡¯s dynamic performance can be studied and optimized (step 2 in Figure 1). Making these kinds of adaptations and trade-offs at this level of abstraction is much more efficient than trying to do it once an RTL description has been generated.

Synthesis-in-the-loop?

Request: to avoid surprises late in the development process, it is desirable to quickly analyze the hardware cost and characteristics of a candidate architecture in terms of its operating frequency, area, and power efficiency.

Solution: ASIP Designer will translate the nML model into fully synthesizable Verilog or VHDL, with full cycle-accurate and bit-accurate control of the hardware (step 3 in Figure 1). Design and verification tools, such as ²ÝÁñÉçÇø¡¯ Design Compiler and VCS, can then be used to implement the ASIP. For example, Design Compiler can be used to check timing closure, and to generate a gate-level description that can be used to predict the circuit¡¯s power requirement and area. Design Compiler will also provide insight into possible routing congestion that may be present in the design, but even a complete physical synthesis including place and route with IC Compiler is possible at strategic points during architectural exploration.

This ¡°synthesis-in-the-loop¡± approach enables educated decisions and avoids surprises later in the design process. If there are problems with the design during implementation, developers can go back to the nML description and adjust it to address the issue (step 2 in Figure 1). Because of the single-source entry in nML, the SDK and RTL will remain in sync.

Figure 1: ASIP Designer tool flow