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Women breaking glass ceilings in technology is a hot topic these days. In fact, the has spearheaded the to encourage women to start and grow careers in semiconductor hardware. Their inaugural technical conference is kicking off right around the corner on September 14 and 15, when Priyanka Joshi, an intern in the ²ÝÁñÉçÇø ²ÝÁñÉçÇø Group, will be presenting her paper, SpyGlass Netlist Level Check on Low-Power DDR Design. Priyanka launched her career at ²ÝÁñÉçÇø last December with a master¡¯s degree in embedded systems, a spirit of curiosity, and a passion for VLSI. We recently sat down with Priyanka to discuss her journey, her aspirations, and her upcoming paper presentation.

Q: What has been a challenge that you faced in deciding to be an engineer?

A: I am the first engineer in my family. I¡¯m the eldest among my sibling and cousins. So, I didn¡¯t have anyone to set an example or advise me on my choice to be an engineer. For instance, there was no one to have an in-depth conversation about my fascination with atoms bombarding a screen and creating a clear image. But, even though I didn¡¯t have those kind of conversations at home, my curiosity drove me forward. I had to know how it worked, so I learned about it.

Q: How did you come to intern at ²ÝÁñÉçÇø?

A: I was in my last semester earning my master¡¯s degree in embedded systems, at , India, when the university had several on-campus and off-campus LinkedIn employment drives. I was looking closely at a few companies from those drives. One of them was ²ÝÁñÉçÇø. This position interested me because it would open a path to working in the VLSI domain. I applied to ²ÝÁñÉçÇø, and I felt very fortunate when I was selected for a ²ÝÁñÉçÇø internship in the Technical Engineering ²ÝÁñÉçÇø Group.

Q: What do you do at ²ÝÁñÉçÇø?

A: Currently, I am working as a technical intern in the DDR-PHY team in the ²ÝÁñÉçÇø Group. I am presently working in the design for testability (DFT) domain for LPDDR and DDR PHY IP. My role in the team is to perform the automatic test pattern generation (ATPG), gate-level simulation runs and work on IP coverage improvements and SpyGlass? DFT (TestMAX Advisor). I also have experience on ²ÝÁñÉçÇø tools like TetraMAX? ATPG and Design Compiler?.

Q: What aspirations do you have in terms of your career trajectory?

A: I would like to learn more about the DFT domain, the one I¡¯m currently working on. I would also like to have more customer interactions to understand their needs better. I aspire to work in high-demand areas, finding solutions for customers¡¯ technical challenges. As the industry dives deeper into smaller chips with reduced transistor size and advanced nodes, say 3nm and 2nm, I want to come up with innovative test solutions without affecting chip performance.

Q: Who has been the most influential person in your education or career and why?

A: My mother works in the medical field. She instilled in me the value of working hard by modeling a great work ethic. There have been many examples through the years of strong people like my mother who have influenced me. Here at ²ÝÁñÉçÇø it has been my manager. This is due to his approach to problem solving. He is open to new ideas, but he has clear vision and strong analytical skills, too. My teammates are also very generous with their time and energy and help me in every aspect of my work. An example of this was when I first started at ²ÝÁñÉçÇø. My team was working on a new product line. There was intense pressure and deadlines throughout the process. Through all of the pressure, they remained open to experimenting and coming up with new ideas. They are amazingly creative technically. The team has been a great inspiration.

Q: Congratulations! You recently had a conference paper accepted to the 2021 WISH Conference. Can you tell us a little bit about your paper, SpyGlass Netlist Level Check on Low-Power DDR Design?

A: Thank you very much. My paper focuses on design rule check debugging and test coverage improvement for high-speed, mixed-signal designs using SpyGlass netlist level checks.

Automotive chips use LPDDR IPs where logic built-in self-test (LBIST) is the primary requirement. To make the design compatible with LBIST, the design should be free from X sources. Identifying and fixing X sources in designs with ATPG and simulation is a long process, and it¡¯s difficult to report all the root causes. Designs can be analyzed and updated for X-free in the pre-placement-and-route stage, eliminating the dependencies over ATPG and simulation flow.

SpyGlass netlist checks are required to grab issues pertaining to scan-insertion, which is not possible at RTL analysis. This will ensure clean synthesis flow and eliminates the issues during timing-annotated simulation.

The paper discusses all the SpyGlass netlist-level methodologies which can be adopted in a DDR PHY for post-DFT checks. The SpyGlass DFT (now called TestMAX Advisor) is a comprehensive process of resolving RTL design issues, so it ensures higher quality RTL/gate netlist with less turnaround time.

SpyGlass netlist checks can analyze X sources and it can find analog macro output port safe states during scan captures. This can be done by writing constraints and with connectivity rule checks to find unexpected behavior and stabilize it early in the design process. We can even run the basic checks at the netlist level. It cannot be performed at the SpyGlass RTL level because scan chains are not inserted at the RTL level and behavior models are not stable, and SpyGlass netlist checks are required to catch all the issues at the pre-place-and-route stages only.