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At advanced nodes, in particular, there are greater process, voltage, and temperature (PVT) challenges to overcome when developing complex chips, whether they are monolithic SoCs or multi-die systems. In-chip PVT monitors have become essential ¡°eyes and ears¡± in these chips, helping to enhance performance and reliability.

²ÝÁñÉçÇø has been at the forefront of chip monitoring solutions, which are part of the ²ÝÁñÉçÇø Silicon Lifecycle Management (SLM) Family. Recently, ²ÝÁñÉçÇø achieved successful tape-out of a PVT Monitor IP test chip on the TSMC N5 and N3E processes, marking a milestone benefiting mutual customers who are ready to design on these advanced nodes. The TSMC N3E process extends the foundry¡¯s 3nm family with enhanced power, performance, and yield, making it ideal for compute-intensive workloads common in applications such as AI, high-performance computing, and mobile. The TSMC N5 process is based on FinFET technology, delivering roughly 20% faster speed and 40% lower power than its N7 process.

Adopted by more than 140 customers around the world, ²ÝÁñÉçÇø SLM PVT Monitor IP has achieved more than 600 design-ins and is available for 28nm down to 3nm. The nature of IP is that it can be sensitive to process and manufacturing technologies, so achieving silicon-proven performance is an important part of establishing trust with chipmakers. Proven IP can save design cycles and costs. Read on to learn more about how monitoring IP can enhance chip outcomes.

Optimizing Silicon Health by Monitoring What¡¯s Happening Inside

Increasing transistor density, multi-die systems, and the need to push silicon performance boundaries are all driving the need to monitor PVT parameters throughout the silicon lifecycle, from in-design to in-field phases. The output of these monitors provides insights sparking actions that chip designers can take to optimize silicon health, making PVT monitoring critical to achieving reliable operation and optimum performance of advanced-node semiconductor devices (such as those with FinFETs and gate-all-around (GAA) transistors).

An in-chip PVT subsystem solution consists of a set of in-chip monitors for process detection, voltage monitoring, and temperature sensing. Embedded monitoring IP provides visibility into the conditions of each of these areas. The data from the PVT monitors feeds into a central management hub (the PVT controller), with data accessible via standard interfaces. The hub is configurable by application and can be integrated into the design flow as well as the architecture of the chip.

PVT monitoring is a major component of SLM, which is becoming more prominent in the semiconductor space. Heterogeneous integration of dies in multi-die systems has put the spotlight on how interconnected chips can be¡ªand why it¡¯s important to ensure that, for instance, the voltage of one die won¡¯t impact the die next to it inside the package. Monitoring is also important for monolithic SoCs, especially at smaller processes, where monitors can flag issues such as IR-drop in the interconnects.

Today¡¯s chips encounter numerous challenges, including:

• Multiple hotspots
• Voltage drops
• Process variation
• Hard-to-predict workloads
• Power uncertainties (too much, or not enough)

Process detectors can help assess and monitor silicon speed, from die to die and across large dies. The data collected can provide insights into silicon aging and for voltage/timing analysis, dynamic voltage and frequency scaling optimization, and speed binning. Voltage monitors measure multiple domain supply voltages and/or IR-drops for validation and optimization of the device¡¯s power distribution network, especially when it is stressed with mission-mode workloads. Temperature sensors enable tight control of the device¡¯s thermal activity.

Chip IP That¡¯s Certified for Quality

²ÝÁñÉçÇø SLM PVT Monitor IP can be used for a wide range of purposes, from real-time thermal mapping to energy/power optimization and silicon assessments for performance enhancements. The IP is also certified by the , which defines a set of minimum IP quality assessments for members of the TSMC IP Alliance Program, a key part of the TSMC Open Innovation Platform? (OIP). With the successful tape-out on the TSMC N5 and N3E processes, ²ÝÁñÉçÇø will be able to share useful post-silicon characterization reports with customers.

As an example of how SLM PVT Monitor IP works, consider an AI use case. With its massive workloads, this chip faces major thermal challenges, with high power distribution and IR-drops. The high power, in turn, limits performance, increasing operating expenses and carbon emissions. SLM PVT Monitor IP can enhance the multi-core utilization of this AI chip, enabling better management of thermal unpredictability with monitors placed close to hotspots, optimized performance/Watt, and the ability to maintain the supply margin for critical logic operation.

Or, consider a multi-die system comprised of dies from different process nodes. Process variability comes into play, as do thermal issues. On-chip monitors can indicate which dies are getting warm and provide actual temperatures, so designers can take meaningful action, such as reducing the voltage, slowing down clock speeds, or even making a certain area dormant for a time.

The larger ²ÝÁñÉçÇø SLM Family of products addresses the challenges around scale and systemic complexity, evolving packaging technologies, and increasing workloads. The products are built on a foundation of enriched in-chip observability, analytics, and integrated automation. To improve silicon health and operational metrics at every phase in a device lifecycle, the products gather meaningful data for continuous analysis and actionable feedback, from in-design to in-ramp, in-test, and in-field operation.