草榴社区

Almost all 3^rd party IP today comes with a throw-away Verilog or C testbenche, with a very limited objective to showing the life in the purchased IP. Architecture of these testbenches is inconsistent between IPs and every IP team uses their own ways to achieve individual IP sanity goals. These test benches require the stripping away and recreation of a completely new verification environment when integrating IPs to SoCs to meet validation and integration sanity objectives. The process of stripping the stock testbench and creating the whole verification setup consumes a lot of time, which essentially is the time eaten away from the verification budget and impacts tape out milestones. More importantly the teams involved in creating these verification setups are different from IP level teams and lack protocol expertise on these IPs and have limited knowledge in configuring these IPs into SoC setups.

Stand-alone IPs and VIPs, support wide range of protocol configurations with expansive test scenarios. User must develop product understanding, protocol expertise, and integration know-how before configuring and validating specific IP configuration and choose from the pool of testcases provided through VIPs to target specific verification requirements.

SoC verification kits leverage expertise and solutions from 草榴社区 IP and 草榴社区 VIP teams to provide ready-to-go UVM based IP-VIP test and debug infrastructure, with curated test cases, scoreboards, and configuration scripts to address the exact need. Having an out-of-box verification kit configured by experts for each of the delivered IP can reduce over-all efforts, can significantly shift-left verification schedule and discover bugs well before IP integration to SoC and at the same time provides an UVM based environment that can be ported to the SoC infrastructure.