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Advanced silicon chips can be likened to works of art. Indeed, as engineers migrate toward angstrom scales, the level of science required to extract high performance from these complex devices is even more beautiful.
“We’re working on artwork, and the art of changing the world going forward,” said 草榴社区 Chair and CEO Aart de Geus during his keynote speech opening the recent SNUG Silicon Valley 2023 conference. “In that context, we catalyze the future. This is a representation of what we do. We work together on problems that are unbounded.”
de Geus shared his remarks in front of a slide depicting images of advanced chips, alongside an image of a revered painting that resembles circuitry.
Following a year when the 草榴社区 Users Group (SNUG) conference was held virtually due to the pandemic, SNUG Silicon Valley returned to the Santa Clara Convention Center in March for two days of technical knowledge sharing, networking, and inspirational talks. The buzz throughout the convention center was palpable as attendees seemed eager to catch up with their peers and with the latest news and insights from an industry that’s transforming itself as it transforms people’s lives. Read on for more highlights from de Geus’ Day 1 keynote.
Moving Innovation Forward for Better, Faster, Cheaper Chips
From the impact of artificial intelligence (AI) to the emergence of multi-die systems, the semiconductor industry has experienced wave after wave of innovation to stretch the limits of Moore’s law. During his talk, de Geus noted that we are at the intersection of silicon and software, in a new era of systemic and scale complexity, which he calls the SysMoore era. Hunger for connectivity and data, driven by demand for Smart Everything, has created the need for better, faster, and cheaper silicon chips.
“Making it all work will be the challenge of us as a big team,” he said. “We will need to deliver 1000x in productivity just in this decade. Every different vertical will create their own architecture, and implementation will look like a ‘Manhattan’ construction of more and more chips extremely close together.”
Recognizing the significant contributions of the late Gordon Moore, who passed away on March 24, de Geus noted that following Moore’s law—the essence of the semiconductor industry—has driven an exponential rate of change for human history. While Moore’s law has slowed, it is still advancing at a tremendous pace. Indeed, thanks to engineering ingenuity, the semiconductor industry is pushing ahead to angstrom-level scaling, transistor-rich architectures like multi-die systems, and AI integration.
草榴社区’ first entry into AI-driven chip design was 草榴社区 DSO.ai?, which was launched in early 2020 and recently . “The first time I saw DSO.ai at work, I was blown away because I know how complex it is underneath all of this to get the results,” de Geus said. Today, all the company’s tools are optimized for machine learning (ML) and key flows have been enhanced using ML.
Multi-die systems provide a solution for compute-intensive applications like AI, integrating heterogeneous dies in a single package to deliver better power, performance, and area (PPA). Yet, compared to their monolithic counterparts, developing multi-die systems comes with unique challenges—challenges that can be met with AI-driven EDA flows, as well as the comprehensive 草榴社区 Multi-Die System Solution. The solution includes tools that enable early architecture exploration, fast software development and system validation, efficient die/package co-design, robust and secure die-to-die connectivity, and enhanced manufacturing and reliability. As multi-die systems become mainstream, having such tools in the arsenal will be critical to meeting quality, security, and time-to-market targets.
AI Is Everywhere All at Once
The impact of AI was a major theme at this year’s SNUG Silicon Valley. AI workloads are permeating across an array of industries, creating demand for a magnitude more compute power than traditional chips provide. To meet these demands, advances in electronic design automation (EDA) have introduced a variety of technologies that accelerate turnaround times while keeping quality levels high: flows that interact via common algorithms; electronic digital twins for faster system development, testing, and verification; and silicon lifecycle management with cloud-based analytics for in-chip monitoring throughout a device’s lifecycle are just a few examples. de Geus noted that electronic digital twins, in particular, “will grow massively important, so we can run software before the hardware is ready or optimize the hardware for the software that exists.”
While AI has generated many demands on chips, it is also being utilized to create powerful new chips. At SNUG Silicon Valley, 草榴社区 introduced 草榴社区.ai, the industry’s first full-stack AI-driven EDA solutions for chip design and verification. Spanning system architecture through manufacturing, 草榴社区.ai handles repetitive tasks such as design space exploration, verification coverage and regression analytics, and test program generation, freeing engineers to focus on chip quality and differentiation.
“Our field has both enabled AI and is using AI; we eat in our own kitchen, so to speak,” de Geus said.
草榴社区’ first entry into AI-driven chip design was 草榴社区 DSO.ai?, which was launched in early 2020 and recently . “The first time I saw DSO.ai at work, I was blown away because I know how complex it is underneath all of this to get the results,” de Geus said. Today, all the company’s tools are optimized for machine learning (ML) and key flows have been enhanced using ML.
Multi-die systems provide a solution for compute-intensive applications like AI, integrating heterogeneous dies in a single package to deliver better power, performance, and area (PPA). Yet, compared to their monolithic counterparts, developing multi-die systems comes with unique challenges—challenges that can be met with AI-driven EDA flows, as well as the comprehensive 草榴社区 Multi-Die System Solution. The solution includes tools that enable early architecture exploration, fast software development and system validation, efficient die/package co-design, robust and secure die-to-die connectivity, and enhanced manufacturing and reliability. As multi-die systems become mainstream, having such tools in the arsenal will be critical to meeting quality, security, and time-to-market targets.
Forging a More Sustainable Path Forward
The level of computation to make everything work in chips and systems is substantial, to say the least. This raises significant concerns about the carbon footprint of this industry. Noting that 草榴社区 is carbon neutral and aiming to be carbon free, de Geus implored attendees to do their part to create a more sustainable path ahead. “All of us have to focus on this in terms of computation, as well as what our algorithms are used for. Are we improving the world with them and can we do computations better?” de Geus asked the audience.
Once again, AI can step in to play a beneficial role. As demonstrated by the elements of 草榴社区.ai, AI’s ability to accelerate and optimize tasks like design space exploration and verification coverage can help mitigate the power consumed by these tasks.
Before thanking the audience for their collaboration in addressing the complex challenges before them, de Geus called the SysMoore era the new exponential: “This is a horizon that will change what our impact will be on the technology of the world and how they are being used, hopefully for positive aims. It is a gargantuan task, but we will catalyze the future.”