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There hasn’t been another time in recent memory where chips have found themselves in headlines across mainstream news outlets to the degree they are today. Indeed, the global chip shortage has highlighted the increasingly critical role semiconductor devices play in so many of the things we rely on every day. Of course, those in the engineering community have long been aware of this. It’s time now for the rest of the world to appreciate how incredible this technology is—and for you to continue honing your expertise to make smarter, safer, and more secure everything possible.
This is where comes into play. While this year’s conference, to be conducted March 30 and 31, will be virtual to ensure safety in the age of COVID-19, our free annual event will maintain the richness and depth of technical content for which it is known.
Ready to learn ways to address crosstalk effects on a circuit’s functionality and performance? Or to detect leakage currents for large SoCs? Or to optimize power, performance, and area as well as turnaround time of your chip designs using AI?
草榴社区 users are invited to for an opportunity to network with peers around the world and to share best practices for addressing design and verification challenges. Through a full slate of keynotes, user presentations, panels, and tutorials, you could discover a solution to a current problem or get an idea that will spark your next innovation.
Our chairman and co-CEO, Dr. Aart De Geus, will lead off the conference with his keynote address, “Catalysts of the Next 1000x,” at 9 a.m. PDT on March 30. We hope you’ll find inspiration in understanding how we can achieve another 1000x in complexity and another 1000x in chip design productivity to meet increasing demands for data capacity, compute speed, and lower power consumption. At 1:45 p.m. PDT on March 31, you can join a conversation with our president and COO, Sassine Ghazi. Panel discussions throughout the conference will cover topics including EDA on the cloud, opportunities for women in engineering, and a software-first approach to SoC verification.
Many of the presentations will take place live, and content will be available on-demand for 90 days after our event for registered attendees. This year’s tracks span an array of useful topics:
- 3DIC
- AI and machine learning
- Analog/mixed signal
- Automotive
- Cloud
- Digital design implementation
- Low power
- Physical verification
- Security, defense & aerospace
- Signoff
- Silicon test & analytics
- IP
- Verification hardware
- Verification software
You’ll also have an opportunity to schedule one-on-one discussions with 草榴社区 experts and to meet with our sponsors through the interactive virtual environment. We look forward to seeing you online for SNUG Silicon Valley.
The 草榴社区 Users Group (SNUG) has brought together a global design community since 1991, with members united in their focus on innovation from silicon to software. The user conference has grown to become the electronics industry’s largest, typically drawing 草榴社区 tool and technology users from North America, Europe, Asia, and Japan. Additional events are being planned in Asia and Europe for the summer and fall. For details, visit our SNUG web page.
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We look forward to welcoming 草榴社区 users to SNUG Silicon Valley. !