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JEDEC officially published the LPDDR4 standard today.  It is very impressive how quickly LPDDR4 was standardized given the comparably long time it took for DDR4 from start to publication.  That is primarily driven by the pace of the smartphone market and the need for increased memory bandwidth year over year which has far outpaced the memory bandwidth growth requirement in the PC SDRAM market. The JEDEC committees responsible for this latest publication should be very proud of their achievement.  Most of the people on these committees have ¡°regular day jobs¡± outside of JEDEC and the support from the various companies involved is also appreciated.

The new standard can be found at the bottom of the page 

LPDDR4 is an interesting DRAM product.  As soon as you get to page 2 of the standard (page 6 of the PDF file), you will notice a ¡°pad order¡± figure.  What may not be so obvious from the diagram is that LPDDR4 is designed to be a single 32-bit wide die with two independent 16-bit wide channels.  This is the first traditional ¡°DDR¡± SDRAM that defines more than one channel for the die.  There are also 64-bit versions of the packages which include two die inside for a total of 4 independent 16-bit wide channels.  Each channel has its own address/command lane.  Since LPDDR4 is a 16n prefetch device (every read/write access 16 words of data), one read or write operate accesses 16 words x 16-bits or 256bits or 32Bytes of data.  That is the same as LPDDR3 which is a 32-bit channel with an 8n prefetch (8 words x 32-bits).  LPDDR4 is designed to operate with independent 16-bit channels which means is it not directly compatible with LPDDR3 which uses 32-bit channels in the 64-bit device or DDR4 which only ever has one channel per device.  SoCs that need to interface to multiple types of DRAMs including LPDDR4 will need to incorporate the flexibility to be optimized for the type of DRAM being used.

Some of the other new features of LPDDR4 include:

• Support for data rates up to 4266Mbps
• A 1.1V operating supply (LPDDR3 and DDR4 are 1.2V)
• The address command lane is very narrow (6 bits for address/command plus clock, chip select, CKE and ODT) and it is single data rate.  Multiple clock cycles are required to transfer commands (4 clock cycles for a read or write)
• Ground terminated signaling (DDR4 & LPDDR3 use VDDQ termination, DDR3 uses midpoint termination)
• A new DMI function which combines data bus inversion and data mask functionality giving you the best of both worlds (with DDR4, only one or the other function can be supported as programmed into the device)
• Two ¡°Frequency Set Points¡± that support switching between two frequencies without ever being in an untrained state

The DRAM vendors are working diligently to make LPDDR4 SDRAM available.  Keep your eyes out for their press releases announcing their products.

²ÝÁñÉçÇø has LPDDR4 IP available for the host devices needing to interface to LPDDR4 and other types of SDRAMs.  Contact us for more information.