草榴社区

We’re already experiencing the effects of our world’s changing climate—devastating wildfires, prolonged droughts, torrential flooding, just to name a few examples. Global energy consumption is increasing, raising carbon dioxide levels and triggering extreme weather conditions. Two key forces driving these trends are the shift to hyperscale datacenters and the explosion of internet traffic.

In short, our world is becoming more digitized, connected, and intelligent. But our planet—and all who call this beautiful place home—is paying the price. What can be done to create a more sustainable, energy-efficient world?

Innovation has led us where we are today, and innovation can lead us toward a more viable path. From the way that we produce and deliver energy to how our electronic systems are designed, there are measures that our industry can take now to ensure that all we’ve built will endure. Read on to learn about four key areas in electronics where the integration of more sustainable practices can yield brighter outcomes for the next generation.

Now Is the Time To Act

While the energy dilemma in the electronics industry seems rather daunting, it is not insurmountable. For one, the servers used in newer hyperscale datacenters tend to be more power efficient than their older counterparts. The power usage efficiency (PUE)—total energy needed divided by energy used for computing—of conventional data centers is about 2.0 compared to about 1.2 for hyperscale data centers, according to a .

In addition, there are several key areas where we can expect better outcomes through the integration of more sustainable practices:

• Energy delivery: Expanding reliance on renewable energy sources, while also locating data centers and networking hubs closer to sources like wind and solar can make a big difference. So can the use of techniques like , such as nickel-zinc.  have already achieved, or plan to soon achieve, 24/7 operation on carbon-free energy.
• Electronics system design: A system-to-silicon approach to the design of electronic systems can reduce power consumption. There are also techniques to enhance energy dissipation, as well as opportunities to use technologies like AI to optimize chips for energy efficiency. Another key aspect of system design is the growing software content from firmware to operating system to application software.
• Silicon technology: The use of energy-efficient materials such as silicon carbide, new transistor devices such as FinFETs, and technologies like silicon photonics and quantum computing can optimize energy usage.
• Operations: Sustainable measures can be applied across the supply chain from chip and system design to electronic design automation (EDA) solutions, IP, fabrication, and package assembly. Many  have set targets for reducing greenhouse gas emissions, and there’s room to do more.

Holistic Approach to Energy-Efficient Design

Let’s take a deeper dive into the area of system design. By applying a holistic, software-driven approach, from architecture through signoff, 草榴社区 customers have demonstrated the ability to achieve >50% energy efficiency.  Let’s have a look at the main design phases to understand how 草榴社区’ solutions have enabled system designers to achieve optimal performance per watt:

• Software: The software does a lot of the heavy lifting, orchestrating power management in the chip and determining critical scenarios for power analysis and optimization during SoC design. It is, therefore, critical to profile and optimize the software to ensure maximum energy efficiency in the SoC.
• Architecture: Power management strategies such as dynamic voltage and frequency scaling (DVFS), power domains, and voltage islands can bring substantial savings. Along with these strategies, macro-architectural tradeoffs for power-performance, as well as IP selection and tradeoffs, can bring the power savings to the 30%-to-50% range.
• RTL: Micro-architectural tradeoffs for clock, data, memory, and glitch power contribute to the savings, as can finding and fixing the RTL power blocks and using tool-guided clock gating, data gating, and memory sizing. The potential power savings here: 15% to 30%.
• Implementation: Applying automatic optimization in areas such as dynamic and leakage power, power integrity with power, performance, and area (PPA) tradeoffs, and power-aware test pattern generation can produce results to the tune of 10% to 15% power savings.
• Signoff: An approach centered on signoff for power and power integrity targets, along with dynamic and leakage power recovery with surgically precise engineering change order (ECO) changes, can yield 5% to 10% power savings.
• Verification: Centering verification efforts on the verification of UPF power intent and UPF-driven functional verification can contribute to greater energy efficiency.

草榴社区 customers have achieved these result ranges using our end-to-end solution for design and verification of energy-efficient SoCs. Software-driven, low-power design solutions, which support UPF (IEEE 1801) low-power intent, can help optimize PPA, while our low-power verification solution can help teams detect and resolve low-power bugs early in the cycle. Technologies like the 草榴社区 DSO.ai? autonomous AI application for chip design uses reinforcement learning to enhance power as well as performance and area for chips. Integrating a portfolio of low-power IP solutions can also help reduce chip power consumption while accelerating time to market. Silicon lifecycle management, providing on-chip sensors for monitoring and analytics, can generate actionable insights about power consumption.