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Victor Moroz

Victor is a ²ÝÁñÉçÇø fellow, engaged in a variety of projects on modeling design-technology co-optimization, FinFETs, gate-all-around transistors, stress engineering, 3D ICs, transistor scaling, cryogenic devices, middle-of-line and back-end-of-line resistance and capacitance, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters, more than 100 technical papers, and over 300 U.S. and international patents. Victor has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, EDTM, and ESSDERC, including having served as a technical chair of SISPAD in 2018 and his current role as editor of IEEE Electron Device Letters.