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Verification IP for JESD204
草榴社区 Verification IP (VIP) for JESD204 provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of JESD204 based designs.
VIP, based on its next generation architecture and implemented in native SystemVerilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.
Highlights
- Native SystemVerilog/UVM
- Runs natively on major simulators
- Built-in protocol checks
- Built-in verification plan and coverage
- Verdi protocol-aware debug
- Extensive error injection
Key Features
- JESD204 A/B/C specification
- 8b10b, 64b66b and 64b80b Link Layer
- Serial data rates up to 32Gbps
- Tx and Rx mode
- Up to 32 lanes
- Up to 256 converters
- Serial/parallel interface (SerDes/Non SerDes Mode)
- Standalone Transport Layer
- Transport and Link Layer test patterns
- Lane skew insertion
- All types of subclass 0, 1, 2
- Lane alignment monitoring, correction and character replacement
- Link re-initialization
- Scrambling
- Sync word support with CRC-12, CRC-3, FEC, and Command Channel
- Soft Sync
- Sync detection and generation clock
- Error injection across Layers:
- Disparity and invalid 8b10b code
- Sync and ILA Sequence Characters
- Sync Header
- CRC-12, CRC-3, FEC parity, Invalid Command Channel data
- EOEMB, EOMB, Pilot bits
