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Highlights

• Native SystemVerilog/Verilog with UVM
• Includes primary, secondary, monitor
• Runs natively on all major simulators
• Built-in UVM sequence library
• Verdi protocol aware debug

Key Features

AXI Interconnect Test Suites Available

• Support for APB4/APB3/APB2
• APB2 Features
  • Primary initiates transfers on the Peripheral Bus
  • Primary supports Write, Read, and Idle transactions
  • Primaryr supports maximum of 16 slave devices
  • Socondary memory response modeled by sequences
• APB3 features
  • Secondary supports wait states using PREADY signal
  • Secondary supports error response using PSLVERR signal
• APB4 features
  • Primary supports write strobe using PSTRB signal
  • Trace Data Transfer (Valid, ready signaling)