Cloud native EDA tools & pre-optimized hardware platforms
草榴社区 VC Replay, previously known as PowerReplay, expedites verification and debug for a range of use cases including design blocks, testbench checkers, SystemVerilog assertions, IP, and ATPG scan patterns. This is alongside its already established support for early RTL power analysis with 草榴社区 PrimePower. VC Replay significantly reduces turnaround time by automating processes that involve localizing a block or an element in the SoC design, capturing the corresponding simulation activity, and creating a new, efficient testbench from this activity. The result is a compact, faster block and testbench that runs 10X-100X quicker, significantly accelerating the verification and debug process.
Focused, extracted simulation that significantly speeds up verification.
The streamlined testbench enables more efficient and faster debugging.
Supports a range of use cases and different scenarios.
Supports early power analysis based on RTL simulation.
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