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In the latest generation of multiple processor SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters, making it a complex verification challenge. System coherency needs to be maintained at various levels, beginning at the cluster level, and continuing, across the cache coherent interconnect and across chips through chip-to-chip gateways. The coherency protocol across interconnects can be AMBA 5, ACE, CHI, CCIX, or CXL. To ensure system level coherency is maintained, a robust cache-coherent checker is required which checks for rules across the system and reports failures on inconsistencies. In addition, the design also goes through multiple revisions adding another level of challenge which requires a scalable testbench that can be reused across projects and from IP to SoC.

In this webcast we will talk about how the ²ÝÁñÉçÇø Verification Family, spanning VCS, Verdi and Verification IP, helped reduce an Arm? Neoverse? N2 core testbench bring-up time by 50%. We will also cover how using scalable protocol converters in the coherency checkers, enabled Arm to address the end-to-end challenges and measure the latency and throughput bottlenecks.