Cloud native EDA tools & pre-optimized hardware platforms
The performance of high-speed interface and silicon interconnects such as UCIe, HBM, and other proprietary interfaces that use a clock forwarding scheme, are critical to monitor over the silicon lifecycle to ensure optimal system level performance.
草榴社区 SLM Signal Integrity Monitor (SIM) IP enables an accurate measurement of these silicon interconnects with real time reporting for analytics. This real-time reporting enables structural lane monitoring and aging related degradation and optional repair (with the use of MTR), of failing lanes to maintain high-speed performance throughout the silicon lifecycle.
The SIM unit (SIMU) has a capture mode for reporting the positive and negative margin of signal edge relative to clock edge. It can support SDR and DDR formats with clock forwarding scheme. Typically, one SIMU is connected at the end of each lane and all the SIMUs form a chain connecting to the SIM controller (SIMC). SIMC provides control /status and test access via 1500/1687.
Figure 1: 草榴社区 SLM Signal Integrity Monitor (SIM) IP
Figure 2: Block Diagram of SLM SIM IP