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Jose Pozo, Chief Technology Officer, Optica

Jose Pozo, CTO of Optica, began the symposium by asserting that photonics is becoming a semiconductor technology. Integrated photonics have found their way into a wide range of products and technologies, which enables the overall communications market representing ~$4.1 trillion or roughly 5% the value of the $94 trillion global economy. Communications services represent the backbone capabilities that enable people to order almost anything online through services like Amazon, stream entertainment to their homes, and hold virtual family reunions using 3D cameras. Pozo noted that integrated photonics are finding their way into a wide variety of applications such as displays, life sciences, industrial tools, lighting, consumer security, and energy generation. In short, photonics, like electronics, are now enabling the global economy.

Pozo pointed out that the single biggest challenge for the wide adoption of integrated photonics is the lack of people to work on photonic-based products. There is a great need for people with physics and science education and there are many opportunities to make a mark in this nascent market. The future for people working in integrated photonics is ¡°bright¡±!

Eric Mounier, Market Research Director, Fellow, Yole Group

Pozo handed the floor to Dr. Eric Mounier, Market Research Director and Fellow of Yole Group. Mounier gave a brief explanation of the work done by Yole Group¡¯s 180+ collaborators and then launched into an explanation of today¡¯s integrated photonics markets and technology trends. Mounier explained that currently 90% of the market for photonics is in optical communications equipment. This market continues to expand with the push from 100 Gbps to 400 Gbps and then to co-packaged photonics with the electrical switch ASICs that will move quickly from 26.6 to 51.2 Tbps.

Silicon-based photonics has found a sweet spot in the 2 km to 80 km data communications market and is being investigated for high-speed optical computing and optical interconnects. The latter is driven by the need to decrease power consumption of HPC resources and to enable disaggregated data centers by reducing latency. However, the real growth in integrated photonics design starts will be in the areas of LiDAR and Fiber Optic Gyroscopes (FOG) for automotive, immunoassays and OCT for healthcare, wearables sensors for Consumer Healthcare and photonic optical computing accelerators for AI and quantum computing and optical interconnects for high performance computing (HPC). Silicon photonic chip revenue is predicted to increase from $152M in 2021 to ~$970M by 2027 representing a 36% CAGR.

Key technical challenges include better laser integration, advanced packaging including chiplet design, through silicon vias (TSVs), photonic interposers, and new materials for even faster photonic modulation. Design tools and methodologies must expand to enable successful design and testing of these new systems.

Dr. Suresh Venkatesan, CEO of POET Technologies

The next speaker, Dr. Suresh Venkatesan, CEO of POET Technologies, introduced POET¡¯s ideas for extending wafer-level chip scale packaging to photonic systems. POET sees assembling, packaging and testing billions of complex heterogeneous systems as a main industry challenge. They are leveraging the idea of heterogeneous integration of best-of-bread chiplets using a common interposer with both electronic and photonic connections. An interposer enables complex systems to be built with a known good die, with interposer interconnect testing being done at the wafer level.

The main idea is to extend the concept of an electrical interposer by adding photonic connections. This has the benefit of eliminating wire-bonds and reducing power consumption and parasitics between chiplets. POET calls this a Photonic Interposer. All processing is done on full wafers, hundreds at a time, in an automated process. The photonic interposer has both electrical and optical layers and can be processed on either 8-inch or 12-inch wafers. A hybrid integration of electrical and photonic chiplets on the interposer is what POET calls an Optical Engine.

A key benefit of this solution is that it uses conventional flip-chip processing technology. Passive electrical and photonic components are printed on the silicon interposer, while active components use hybrid integration as chiplets onto the interposer. The photonic interposer supports two non-interacting optical waveguide layers sandwiched between electrical layers. Light can be coupled in and out, either vertically or horizontally. The technology supports through-silicon-vias (TSVs), so both sides of the interposer can be used. POET has also architected in thermal isolation and management into the photonic interposer to move heat away from sensitive photonic elements such as lasers and resonant devices. Venkatesan showed examples of small-form-factor 100G and 400G transceivers with spatial division multiplexing from 8 to 16 channels running from 1.6 Tbps to 3.2 Tbps, representing a 75% reduction in size compared to designs using discreet components. Venkatesan also pointed out that signal integrity is much better due to lack of wire bonds and metal traces. Since the signal integrity is better, POET is now investigating the idea of removing the DSP altogether, which has the potential to eliminate 6 to 8 watts of power consumed by the DSP.

Dr. Duncan MacFarlane, Professor at Southern Methodist University

Dr. Duncan MacFarlane, Professor at Southern Methodist University (SMU), gave a brief history of his work with integrated photonics, including a two-dimensional active photonic lattice that was used in volumetric displays in 1994. More recently, MacFarlane has been working on small trench-based 1¡Á2 and 2¡Á2 photonic couplers and splitters that represent a 25X area reduction over standard architectures. These couplers and splitters are used to make Hadamard and Christensen gates used for quantum computing.

Mitch Thornton, Cecil H. Green Chair of Engineering and Professor, Southern Methodist University

Professor Mitch Thornton, also of SMU, presented a gate model of quantum computing called MustangQ, which can be used both as a quantum compiler and as a quantum computing design automation tool. MustangQ enables the user to capture a specification for their quantum design using Verilog RTL. SMU uses the ²ÝÁñÉçÇø Design Compiler synthesis tool and MustangQ to synthesize the design to combination logic, and then map that representation onto a user-specified gate cell library. Output from this step can be sent directly to a quantum computer to be run, or it can be used to create a quantum computing Q-ASIC chip. Technology mapping is done to a specific quantum library of cells belonging to a given quantum computing architecture. MustangQ supports placement and routing of these photonic circuits based on the connectivity derived from the synthesis steps. This is extremely exciting work, and we look forward to seeing the results once devices are manufactured at AIM Photonics foundry.

Dr. Saeed Fathololoumi, Tech Lead for Co-Packaged Optic Photonic Integrated Circuits, Intel

It is said that quantum computers will be thousands of times faster than today¡¯s best computers. Imagine the data bottlenecks that will develop trying to feed these computing monsters. The next presentation at the symposium, given by Dr. Saeed Fathololoumi, Tech Lead for co-packaged optics and photonic ICs (CPOs and PICs) at Intel, was a perfect follow up to the quantum computing discussion.

Fathololoumi¡¯s talk was titled, ¡°Integrated Photonic Circuits for Optical Compute Interconnects.¡± He started his discussion about optical compute interconnects (OCIs) by reviewing the history of compute and processing rates. In the mid-2000s, single thread and process rates saturated, and the industry shifted to integrating cores to allow more parallel computing to increase compute performance. As a result of a massive increase in the number of processor cores, the compute bottleneck moved to off-chip I/O bandwidth as well as a jump in power needed to drive the off-chip signals between clusters of processors. Soon after, the power required for chip I/O and interconnect surpassed the power needed for computation. Fathololoumi concluded that bandwidth density and signal latency must improve dramatically and that OCI is seen as an enabler to meet these needs.

Fathololoumi noted that in Intel¡¯s vision, electronic (EIC) and photonic chiplets are kept separate to allow for use of best of breed technology from each domain. 3D stacking is employed to enable low loss, high bandwidth communications between the EICs and PICs. EICs contain gearbox logic, signal to optical format conversions, and driving and control components, while the PICs handles all transmit, receive and fiber coupling. Intel integrates lasers and SOAs on the PICs for lower power consumption and better overall system reliability.

System benefits include the ability for compute scale-up and resource pooling, greater package yields for pluggable photonics right to the EICs, wafer-based test for known good die before packaging, lower power, higher bandwidth density, lower costs and higher reliability when integrating all photonic components on the same die.

Fathololoumi presented a block diagram of a typical OCI architecture with 8 lasers using 200GHz spacing modulated and filtered by micro-ring resonators. Polarization management and signal amplification is done on the receive side after which the signal is interleaved into even and odd channels and sent to separate photo diodes. Fathololoumi also spoke to technologies for use beyond 32Gbps and noted other industry activities such as the DARPA PIPEs program and efforts by Ayar Labs and NVIDIA on similar architectures. He rounded out his discussion with an OCI scaling roadmap showing overall scaling going from 1 Tbps/fiber when using 64G NRZ with 16 wavelengths to greater than 10 Tbps/fiber when using 128G PAM4 dual polarity and 64 wavelengths.

Vikas Gupta, Senior Director of Product Management, Silicon Photonics, Global Foundries

Vikas Gupta, Senior Director of Product Management for Silicon Photonics at GlobalFoundries, was the next speaker. Gupta compared the development paths of integrated electronics and photonics. He noted that CMOS RF performance peaked at about the 45nm CMOS node. As a result, GlobalFoundries chose this node as the basis for their photonic offering, which is comprised of the industry¡¯s only monolithic silicon-based platform that incorporates high-speed RFCMOS and photonics on the same die. This 300mm wafer process is called GF Fotonix and was qualified in early 2022. Process design kits (PDKs) are available for multiple design tool platforms. The PDK includes active and passive components with a wide variety of devices targeted to data center communications applications.

According to Gupta, there are four elements that are needed for a complete photonic design to manufacturing eco-system, those being volume PIC manufacturing, EDA, IP and Packaging. GlobalFoundries has been working diligently over the last several years with leading EDA suppliers to field a robust photonic PDK that can be used with EDA design tools for circuit-level photonic IC design. The PDK acts as an implicit contract between the foundry and the customer suggesting that whatever you design with the PDK will indeed be manufacturable. The PDK also acts as a level of abstraction that allows designers to work at the circuit level instead of the device level, enabling more complex designs to be created and manufactured.

For photonic IP eco-system, Gupta noted the PDK acts as the foundation for an IP ecosystem by making available pre-characterized building blocks in the form of programmable layout cells, symbols, and simulation models. However, there is still an opportunity for companies to create application-specific IPs such as TIAs, modulation drivers, DAC/ADC, photonic DWDM filters with heater controls, and eventually chiplets created for specific end applications segments.

Regarding packaging, Gupta sees packaging costs and industry readiness for high-volume manufacturing as the major roadblock for full market adoption of integrated photonics. GlobalFoundries is working on packaging-related items to reduce the barrier to adoption. Examples of this include low-cost passive fiber attach, reflow compatible assembly w/ Cu-P & Cu u-pillars, 2.5D compatibility, direct laser attach, JEDEC specs where appropriate and a commitment to enable a microelectronic OSAT model for their customers¡¯ packaging needs.

Yuval Shay, Product Marketing Director Photonic ²ÝÁñÉçÇø, ²ÝÁñÉçÇø

The final speaker of the day was Yuval Shay, Director of Silicon Photonics Product Management at ²ÝÁñÉçÇø. Shay reiterated that ²ÝÁñÉçÇø sees integrated photonic design starts in all the market segments mentioned by the previous speakers and echoed Pozo¡¯s comments about the need for more photonic design engineers. Shay noted that the ²ÝÁñÉçÇø photonic design platform was purposefully architected to enable CMOS designers the ability to push into integrated photonics using a familiar AMS-like design flow. Examples of this include the use of schematic-driven-layout, simulation with back-annotated effects from layout, electrical and photonic layout-vs-schematic checks, and design rule checking tuned for curvilinear layouts.

Shay noted that almost all photonic ICs end up being co-designed and sometimes co-packaged with electrical ICs. The co-design and co-packaging of EICs and PICs bring additional challenges that must be met by EDA suppliers and ²ÝÁñÉçÇø is working on these challenges with leading customers. Shay highlighted unique features of the ²ÝÁñÉçÇø photonics solution, including:

• Photonic versus electronic aware editors
• Automated all angle abutment for curvilinear layout
• Automated waveguide connections, with constraint driven waveguide bus connections
• Accurate post-layout photonic simulations using back annotated waveguide connections
• photonic circuit & system-level simulation
• Electrical / optical so-simulation
• Link-based simulations with models for drivers, receivers, fiber, optical amplifiers, and analysis
• Custom device tool flow that designers to augment a foundry PDK with their own devices
• Maxwell¡¯s Equations solvers for device characterization and CAD view generation
• Signoff quality DRC and LVS to ensure manufacturable devices

Shay wrapped up his presentation by revealing that ²ÝÁñÉçÇø has the world¡¯s largest software development team working on all-things optics and photonics.  ²ÝÁñÉçÇø recognized early on the importance of optics and photonics and has steadily acquired technology and talent for more than a decade. ²ÝÁñÉçÇø offers a wide spectrum of design solutions for imaging, illumination, photonic process and device co-optimization, circuit and system-level integrated photonics and electronic-photonic co-packaging.

Shay concluded the seminar by noting that ²ÝÁñÉçÇø will be hosting a series of online tech talks over the coming months on topics that include:

• Passive and active photonic device generation
• Script-based schematic driven layout
• Electro-optical co-simulation of a PAM4 transmitter