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A System-on-Chip (SoC) is an integrated circuit that contains all the required electronic circuits for a fully functional system. We’ve already discussed the basics of SoCs and why they are so critical for the next generation of computing and established many advantages from miniaturization to power efficiency to production methods. However, in this article, we’ll be delving into what exactly goes into creating a System on Chip design.
SoCs seek to integrate as many computer components as possible onto a single piece of hardware. This integration typically includes the CPU, GPU, memory interfaces, possible cellular communications methods, and other components onto a single die.
Let’s take a close look at each.
SoCs have a variety of blocks that require sending data and instructions and thus require communication subsystems. For a while, traditional data bus architectures were used to connect the different blocks of the SoC. For example, ARM’s royalty-free Advanced Microcontroller Bus Architecture (AMBA) was a common standard. However, computer buses have limited scalability and support only tens of cores.
Wire delay is not scalable due to smaller miniaturization; this results in system performance not scaling with the number of cores. For this reason, the SoC’s operating frequency must decrease to remain sustainable. This fact, coupled with more wires consuming more electrical power, has led to adoption of network-on-chip (NoC) technology.
With NoC technology, advantages include application and destination-specific routing, better power efficiency, and reduced bus content. Newer NoC architectures are constantly being developed. For example, distributed computing network topologies such as torus, hypercube, mesh, and tree networks are increasingly popular. NoC architectures can efficiently meet the power and throughput needs of SoC designs.
Designing SoCs involves hardware and software to control the processor, peripherals, and interfaces. A strong design workflow develops hardware and software simultaneously in an architectural co-design method.
Concerning hardware, as with integrated circuit design in general, many SoCs are developed using hardware component IP core specifications, known as blocks. Hardware blocks are created using EDA tools and can be classified into the following categories:
On the software side, SoCs are designed with high-level programming languages (MATLAB, C++, etc.) and are converted to RTL designs through high-level synthesis tools. These algorithmic synthesis tools allow designers to model and synthesize the system, circuit, software, and verification levels in a single language.
After architecture is defined, new hardware elements are written and synthesized into register transfer level (RTL), defining the circuit behavior and then connected in HDL, creating the full SoC design.
The SoC must be verified for validation before being manufactured in a foundry, in a process known as functional verification. The verification process accounts for a large portion of the chip design life cycle —up to 70%. Once the chip is fully verified to work as intended, it is sent to the foundry for mass production.
草榴社区 is the industry’s largest provider of electronic design automation (EDA) technology used in the design and verification of semiconductor devices, or chips. With 草榴社区 Cloud, we’re taking EDA to new heights, combining the availability of advanced compute and storage infrastructure with unlimited access to EDA software licenses on-demand so you can focus on what you do best – designing chips, faster. Delivering cloud-native EDA tools and pre-optimized hardware platforms, an extremely flexible business model, and a modern customer experience, 草榴社区 has reimagined the future of chip design on the cloud, without disrupting proven workflows.
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Sridhar Panchapakesan is the Senior Director, Cloud Engagements at 草榴社区, responsible for enabling customers to successfully adopt cloud solutions for their EDA workflows. He drives cloud-centric initiatives, marketing, and collaboration efforts with foundry partners, cloud vendors and strategic customers at 草榴社区. He has 25+ years’ experience in the EDA industry and is especially skilled in managing and driving business-critical engagements at top-tier customers. He has a MBA degree from the Haas School of Business, UC Berkeley and a MSEE from the University of Houston.