Cloud native EDA tools & pre-optimized hardware platforms
Ed Sperling's article "" highlights an evolving trend in chip design. Chipmakers are increasingly adopting use case modeling techniques to better understand the interplay between software and hardware, particularly focusing on system performance and energy efficiency.
As multicore System on Chips (SoCs) become more software-intensive, the interactions within them grow more complex. For system designers and SoC architects, early prediction of their product’s performance against rigorous application requirements is key. To achieve this, system-level goals need to be quantified using “Key Performance Indicators” (KPIs). KPIs are vital for defining system requirements clearly and concisely, especially from the application use case perspective. Common KPI examples include:
Can today's software modeling techniques fully execute critical use cases and their KPIs for early analysis, without running the actual software? The answer is a resounding YES. Application workload models, like task graphs, capture the processing and communication demands of use cases. This allows comparison of architecture simulation results with target KPIs in an efficient and automated manner, enabling earlier specification verification.
An example is shown in the next graphic, where three different SoC architecture configurations are simulated in 草榴社区 Platform Architect. All simulations use the same workload model - a task graph of the Chrome Browser in an Android environment. The charts depict CPU load over time for the browser use case, with each color indicating the load from an individual Android process. The data shows how adding processing resources improves the system's ability to execute the browser task. Importantly, the results also indicate where system optimization can further reduce power and cost while still meeting KPIs.
After finalizing the SoC architecture, tracking critical application use cases and their KPIs throughout the development process ensures that system specifications are met. Task graphs, representing workload models rather than actual software, facilitate collaboration with semiconductor suppliers by providing executable specifications of use cases and their KPIs.
In sum, leveraging Key Performance Indicators, use case workload modeling, and early architecture analysis is crucial. This approach helps in closing the loop on specifications for next-generation architectures, ensuring that they meet the set performance standards and deadlines.