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This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. 草榴社区 provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos.
The Verification demo was centered around the PCIe 5.0 VIP acting as a Root Complex talking to our Integrated IP for PCIe 5.0 Endpoint. We specifically highlighted one of our PCIe 5.0 tests from the UVM source code test suites. The demo walked users through linkup and training including equalization. The test executed configuration of the BAR and then a series of DMA transfers. The demo also showcased natively integrated Verdi Protocol Analyzer for easy and fast transaction level debug.
In addition to demonstrating the debug capabilities of Verdi Protocol Analyzer, the symbol log, the transaction log, the simulation log file, and the ASCII signals were also shown to reveal the highly effective debug capabilities provided by 草榴社区 VIP. These built-in tools, along with the comprehensive test suite consisting hundreds of tests and use of the latest verification technology, will help to quickly verify a complex PCIe design. Click below to watch the demo video.
草榴社区 also showcased three DesignWare IP demos at this event. The Advanced Debug, Error Injection, and Statistics for PCIe 4.0 demo highlighted advanced capabilities of the DesignWare IP for PCIe 4.0 including reliability, availability, and serviceability (RAS) along with debug, error injection and, statistical monitoring. These capabilities are vital to a range of applications such as automotive and storage. The DesignWare IP for PCIe 5.0 at 32GT/s demo showed how designers can successfully reach PCIe 5.0 32GT/s data rates with 草榴社区’ DesignWare Controller IP for PCIe. It also showed how using the 草榴社区 coreConsultant tool helps designers make performance, power, and area tradeoffs, necessary considerations for applications such as artificial intelligence, cloud computing, storage, and networking. Click below to watch the demo video.
The DesignWare PHY IP for 16GT/s and Beyond demo showed a transmitter and receiver connectivity between 草榴社区’ 16-nm and 7-nm PHYs for PCI Express across a lossy channel. 草榴社区’ flexible graphical user interface was used to configure the PHY for different speeds and equalization setting. The GUI displayed the signal eye, lane margining results, and bit error rate using bathtub curves. Click below to watch the demo video.
The team enjoyed interacting with the attendees and was excited to see several new designs adopting PCIe 5.0. We look forward to next year’s event, where we hope those customers will have had their first tape outs and anticipate the PCIe 5.0 spec will be ratified.
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Sep 12, 2024
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