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PCIe protocol has rapidly evolved over the last 15+ years, from a raw bit rate of 2.5GT/s in 2002 with Gen1, to today¡¯s 32GT/s with this latest PCIe 5.0. The adoption of the PCI Express from desktop computing to cloud, growing demand for increased throughput, reduced latency, footprint, and power have been driving the innovation in the PCIe standard.

Significant new features have been added to PCIe 5.0, such as new Equalization Options and Alternate Protocol Negotiation (APN), to meet the system requirements with predictable and stable bandwidth, latency and power (see below).

²ÝÁñÉçÇø VIP and source code Test Suite for PCIe 5.0 has been adopted broadly across industry leaders working on next generation cloud, data center, 5G, and HPC designs since the initial conception of the specification. VIP capabilities and tests suites are enhanced and matured working with these leading PCIe Gen5 adopters to systematically mitigate their design implementation risk of the new features published in each specification draft (see below) .

²ÝÁñÉçÇø VIP delivers enhanced performance and verification productivity gains through its native SV/UVM implementation and native integration with ²ÝÁñÉçÇø VCS and Verdi Protocol Analyzer. ²ÝÁñÉçÇø VIP is delivered with built-in functional coverage and source code Gen 5 Test Suite to accelerate the verification closure and achieve tape-out of first-pass quality designs.

Join ²ÝÁñÉçÇø PCIe experts at PCI-SIG Developers Conference on June 18-19, 2019 at the Santa Clara Convention Center. Visit the ²ÝÁñÉçÇø booth to see the complete DesignWare Controller, PHY, and Verification IP Solution and to network with experts. ²ÝÁñÉçÇø will also provide several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP and source code Test Suites.

For more information on ²ÝÁñÉçÇø VIP, please visit .